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TMS320F28388D: The configuration of QPOSSLAT

Yuta Tsukioka
Prodigy 10 points
Part Number: TMS320F28388D


I'm attempting to trigger the latching of the position counter's value with the ADCSOCA, but the value of QPOSSLAT remains at 0 without updating.

Is there any part of the configuration that is incorrect, or are there any other registers that should be checked?

EQep1Regs.QEPCTL.all=0x9258
EPwm1Regs.ETSEL.all= 0x3a03
QEPSTROBESEL = 0x002
ADCSOCOUTSELECT = 0x001
EPwm1Regs.ETSOCPS.all=0x0101



  • 0
    TI__Mastermind 26446 points

    Hi Yuta,

    The configuration for eQEP and ePWM seem correct. Could you verify that your PWM signal is being output correctly on pins? I see you have

    EPWMxSOCA being generated on event time-base counter equal to period and EPWMxSOCB enabled when event time-base counter equal to zero.

    Do you have set the TBPRD for ePWM? Have you set TBCLKSYNC for the ePWM modules to start the TBCTR for the PWM modules? If the PWM module is not running, there will be no events being generated.

    Best regards,

    Ryan Ma

  • 0 in reply to Ryan Ma
    Prodigy 10 points

    Hi Ryan,
    Thank you for your comment.
     I have confirmed that the ADCSOCA signal is being output using OUTPUTXBAR5. However, even when changing the settings from X-Bar to eQEP, QPOSSLAT does not get updated.



    Ch2 : EPWMxSOCA (OUTPUTXBAR5)
    Ch4 : PWM1


    Best regards,
    Yuta

  • 0 in reply to Yuta Tsukioka
    TI__Mastermind 26446 points

    Hi Yuta,

    Are you sure the register view is on continuous refresh? Could you also show me you're QDECCTL:IGATE configuration? Could you double check to see if the IGATE is set to 1?

    EQep1Regs.QEPCTL.all=0x9258 : // 10_01_00_10_0_1_01_1_0_0_0
    // FREE_SOFT: 10
    // PCRM: 01
    // SEI: 00
    // IEI:  10
    // SWI: 0
    // SEL: 1
    // IEL: 01
    // QPEN: 1
    // QCLM: 0
    // UTE: 0 
    // WDE: 0
    Best,
    Ryan Ma
  • 0 in reply to Ryan Ma
    Prodigy 10 points

    Hi Ryan,

    Thank you for your information.
    The register view is continuously being updated.I have set QDECCTL:IGATE to 0 because I want to use the QS signal.


    EQep1Regs.QEPCTL.all=0x9258 : // 10_01_00_10_0_1_01_1_0_0_0
    // FREE_SOFT: 10
    // PCRM: 01
    // SEI: 00
    // IEI:  10
    // SWI: 0
    // SEL: 1
    // IEL: 01
    // QPEN: 1
    // QCLM: 0
    // UTE: 0 
    // WDE: 0
    EQep1Regs.QDECCTL.all = 0x0000
    EQep1Regs.QEPSTROBESEL.STROBESEL = 0x0002

    Best regards,
    Yuta
  • 0 in reply to Yuta Tsukioka
    Prodigy 10 points

    Hi Ryan,
    Setting EQep1Regs.QEPSRCSEL.bit.QEPSSEL to 1 resulted in the update of QPOSSLAT. However, the explanation for QEPSSEL was not found.
    How is QEPSSEL being used? Can you provide a block diagram?

    Best regards,
    Yuta

  • 0 in reply to Yuta Tsukioka
    TI__Mastermind 26446 points

    Hi Yuta,

    Apologize for the confusion, I am going to see if we can add a block diagram for this as it is an important step in configuring the Position Counter Latch. 

    I will provide an update once I get confirmation on this functionality. Thank you for bringing this to our attention.

    Best,

    Ryan Ma

  • 0 in reply to Ryan Ma
    Prodigy 10 points

    Hi Ryan,

    Have you been able to confirm this functionality?
    When can I expect a response?

    Best regards,
    Yuta

  • 0 in reply to Yuta Tsukioka
    TI__Mastermind 26446 points

    Hi Yuta,

    Apologize for the late response. You are correct and I have taken action to note this in the TRM.

    Best,

    Ryan Ma