TMS320F28384D: The CM4 MPU

Hi Luke,

Below is the definition of PRIVDEFENA  bit from ARM Generic User Guide.

If you have MPU enabled and this bit is 0 then default memory map is disabled and user need to define proper region in MPU to enable access else a fault will be generated.

Regards,

Vivek Singh

Vivek,

What is the default memory map? Is it the linker command file in project?

When I set PRIVDEFENA bit and then application code branches to faultISR right away, how can user define proper region in MPU to enable access? Is there any suggested process to do that?

Regards,

Luke

Luke,

Default memory map is defined in our device datasheet. When user enables MPU then memory map is defined as per MPU setting. Using PRIVDEFENA bit user can always enable default memory map for privileged  software irrespective of MPU settings.  There is lot's of online material available on how to setup the MPU (like this one - https://blog.feabhas.com/2013/02/setting-up-the-cortex-m34-armv7-m-memory-protection-unit-mpu/)

Vivek Singh

Vivek,

In our example project mpu_ex1_fault_handling, we have below NOP instructions to avoid repeated fault generation, means that application code will keep issuing fault ISR without those NOPs.

//
// Adding NOPs to return execution to any of these NOPs and not the above
// statement which generated fault. This has been done to avoid repeated
// fault generation due to above memory write operation to protected memory.
//
NOP;
NOP;
NOP;
NOP;

However, if we use MPU function, we don't know when software will violates MPU rule and generate fault ISR, it is impossible we add the NOPs in advance and avoid repeated fault generation.

Any comments on this situation please?

Regards,

Luke

Luke,

We need to avoid the fault in Ist place. I am not clear why adding NOP while avoid fault. User need to have proper MPU setup to avoid these fault unless the instruction is trying to access protected region. 

Vivek Singh

Vivek,

Adding NOPs and the comments is from our example, please check it.

According to my customer's evaluation result, if they try something to violate MPU rule in main loop, the NOP is not necessary. However, if they add code to violate MPU rule in ISR, then the NOP is necessary so that application code is able to return from faultISR.

We have no idea what makes this difference? Please check and advise your comments, thanks for help.

Regards,

Luke

Luke,

Let me check with our SW team and get back to you.

Vivek Singh

Hi Vivek,

As MPU sample code blow, 

When illegal memory access happened, MPU ISR  is executed,

Sample code use updating the return address in the stack to continue the code execution (back to the illegal memory access next line ),

Do you have suggestion for MPU ISR fault handling(Without NOP, back to the illegal memory access next line ) ? 

//
// Once ISR is executed the execution returns to the instruction that
// caused the fault and this again leads to another fault.
// Updating the return address in the stack so that the handler returns
// to any of the NOP instructions added in the example code.
// This is being done for demonstration purpose only. The application code
// should handle the fault as per requirement.
//
asm(" ldr r0, [sp, #0x18]");
asm(" add r0, r0, #4");
asm(" str r0, [sp, #0x18]");

Regards,

ChanHan

Hi,

I have looped in our SW expert on this. Meanwhile you can look at online material available on this topic - https://developer.arm.com/documentation/ddi0363/e/level-one-memory-system/fault-handling?lang=en

Regards,

Vivek Singh