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TMS320F28P650DK: EtherCat electrical diagram and clock generation

Ettore Marroni
Prodigy 200 points
Part Number: TMS320F28P650DK


Hello TI Support Team, 

I have take a look to the following TI documents

  • C2000Tm F28P65x Series LaunchPadTm Development Kit
  • TMS320F28P65x Real-Time Microcontrollers , Technical Reference Manual
  • F28P65X Control Card

and I would like to ask your support about some points.

Based on my understanding ESC EtherCat runs inside F28P65: please can you confirm ?

Further, I find four options for EtherCat electrical diagram: please refer to the next options.

Option 1

One oscillator provides clock to ESC and PHYs devices, as shown on the next pictures.

 

 

  

Option 2

One oscillator provides clock to ESC.

ESC provides clock to PHY devices through GPIO154, as shown on the next pictures.

 

  

 

Option 3

One oscillator for the EtherCat PHYs

One oscillator for the Dsp 

Ethercat PHYs 

 

 

 

 

CPU oscillator

 

Option 4

Based on my understanding, user manual doesn’t describe this configuration: please look at on the "Questions part".

 

 

 

Questions

Assuming that my logic board works on electromagnetic harsh environment, can you suggest the best Ethercat electrical diagram ?

Regarding the PCB layout, assuming that we do not want sharing high frequency clock signal through a long net, can you also suggest the best electrical diagram ?

F28P65 peripheral manual, doesn’t state about the clock generation or distribution shown by the electrical diagram on option 3: am I correct ? If yes, why ?

Given the configuration shown on “Option 4” , please can you describe:

    1. the features of MII_Tx_CLK_port1 and MII_Tx_CLK_port0
    2. how these two optional connections affects the clock generation ? I mean is the clock over the red net still necessary ?

 

Thank you very much for your support,

Ettore

  • +1
    TI__Mastermind 45606 points

    Hi Ettore,

    Ettore Marroni said:
    Based on my understanding ESC EtherCat runs inside F28P65: please can you confirm ?

    That's correct.

    Ettore Marroni said:

    Assuming that my logic board works on electromagnetic harsh environment, can you suggest the best Ethercat electrical diagram ?

    Regarding the PCB layout, assuming that we do not want sharing high frequency clock signal through a long net, can you also suggest the best electrical diagram ?

    Option #1 is our best recommendation. We suggest users to have the C2000 ESC and two Ethernet PHYs to share the same external 25MHz single-ended oscillator with +/-25ppm or less (per Beckhoff specifications). Also recommend including a clock-buffer to ensure clock signal integrity to all three devices, this is what we implement in our LaunchPad and ControlCARD. You can refer to those schematic and PCB designs for reference.

    Ettore Marroni said:
    F28P65 peripheral manual, doesn’t state about the clock generation or distribution shown by the electrical diagram on option 3: am I correct ? If yes, why ?

    Option #3 you show is not advised. Beckhoff requires that the ESC and two Ethernet PHYs share the same clock source.

    Ettore Marroni said:

    Given the configuration shown on “Option 4” , please can you describe:

      1. the features of MII_Tx_CLK_port1 and MII_Tx_CLK_port0
      2. how these two optional connections affects the clock generation ? I mean is the clock over the red net still necessary ?

    The MII_TX_CLK_port signals are not related to the 25MHz clock source. You will always need to provide the 25MHz clock source to the PHYs in some way.

    I honestly had never noticed the MII_TX_CLK pins were documented as optional. This is not something I've tested with in the past and we always have included the connection in our designs. It seems we even 'strongly recommend' users to do the same in the TRM.

    Best,

    Kevin