TMS320F28379D: HRPWM issue

user4913395

Part Number: TMS320F28379D

Hello,

I'm working on two multi-phase buck converters driven in complementary manner to achieve bipolar output voltage between two outputs. Thus, at 0.5 duty cycle the output voltage is 0. When performing a sweep from 10% to 90% duty on output voltage some nonlinearities can be observed. The interval between them corresponds to the epwm coarse step size. These artifacts become progressively more pronounced only as we approach the two extremes (image below) but are not seen in the middle region. MEP is regularly updated in background loop, duty cycle range limitation also should not be an issue since we are always far from 0 or 100%. Any hint what could be the cause?

Thanks

Fullscreen

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
void EPWM_init()
{
    uint16_t j = 1;
    uint16_t phase_shift1 = 2;
    uint16_t phase_shift2 = EPWM_TIMER_TBPRD / 3 + 2;
    uint16_t phase_shift3 = 2 * (EPWM_TIMER_TBPRD / 3) + 2;
    // Disable sync(Freeze clock to PWM as well). GTBCLKSYNC is applicable
    // only for multiple core devices. Uncomment the below statement if
    // applicable.
    //
    // SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC);
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    EPWM_disableADCTrigger(EPWM1_BASE, EPWM_SOC_A);
    for(j = 1; j < 7; j++)
    {
        HRPWM_selectPeriodLoadEvent(ePWM[j], EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

void EPWM_init()
{

    uint16_t j = 1;

    uint16_t phase_shift1 = 2;
    uint16_t phase_shift2 = EPWM_TIMER_TBPRD / 3 + 2;
    uint16_t phase_shift3 = 2 * (EPWM_TIMER_TBPRD / 3) + 2;

    // Disable sync(Freeze clock to PWM as well). GTBCLKSYNC is applicable
    // only for multiple core devices. Uncomment the below statement if
    // applicable.
    //
    // SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC);
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    EPWM_disableADCTrigger(EPWM1_BASE, EPWM_SOC_A);

    for(j = 1; j < 7; j++)
    {
        HRPWM_selectPeriodLoadEvent(ePWM[j], EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO);

        // Set TBCLK
        EPWM_setTimeBasePeriod(ePWM[j], EPWM_TIMER_TBPRD);
        EPWM_setPhaseShift(ePWM[j], 0U);
        EPWM_setTimeBaseCounter(ePWM[j], 0U);
        
        // Set counter mode
        HRPWM_setTimeBaseCounterMode(ePWM[j], EPWM_COUNTER_MODE_UP);
        HRPWM_setClockPrescaler(ePWM[j], EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

        // Set Initial Compare values
        HRPWM_setCounterCompareValue(ePWM[j], HRPWM_COUNTER_COMPARE_A, (EPWM_TIMER_TBPRD/2 << 8));
        HRPWM_setCounterCompareShadowLoadMode(ePWM[j], EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_PERIOD);
        EPWM_enableGlobalLoadRegisters(ePWM[j], EPWM_GL_REGISTER_CMPA_CMPAHR);
        if(j != 1)EPWM_setupEPWMLinks(ePWM[j], EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A);

	// Set actions
        if(j%2 == 0){
            HRPWM_setActionQualifierAction(ePWM[j],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
            HRPWM_setActionQualifierAction(ePWM[j],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
        }
        else{
            HRPWM_setActionQualifierAction(ePWM[j],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
            HRPWM_setActionQualifierAction(ePWM[j],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
        }

        HRPWM_setMEPEdgeSelect(ePWM[j], HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_FALLING_EDGE);
        HRPWM_setMEPControlMode(ePWM[j], HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL);
        HRPWM_setCounterCompareShadowLoadEvent(ePWM[j], HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_PERIOD);
    }

    // Phase shift	
    EPWM_enablePhaseShiftLoad(EPWM2_BASE);
    EPWM_selectPeriodLoadEvent(EPWM2_BASE, EPWM_SHADOW_LOAD_MODE_SYNC);
    EPWM_setPhaseShift(EPWM2_BASE, phase_shift1);
    EPWM_setTimeBaseCounter(EPWM2_BASE, phase_shift1);

    EPWM_enablePhaseShiftLoad(EPWM3_BASE);
    EPWM_selectPeriodLoadEvent(EPWM3_BASE, EPWM_SHADOW_LOAD_MODE_SYNC);
    EPWM_setPhaseShift(EPWM3_BASE, phase_shift2);
    EPWM_setTimeBaseCounter(EPWM3_BASE, phase_shift2);

    EPWM_enablePhaseShiftLoad(EPWM4_BASE);
    EPWM_selectPeriodLoadEvent(EPWM4_BASE, EPWM_SHADOW_LOAD_MODE_SYNC);
    EPWM_setPhaseShift(EPWM4_BASE, phase_shift2);
    EPWM_setTimeBaseCounter(EPWM4_BASE, phase_shift2);

    EPWM_enablePhaseShiftLoad(EPWM5_BASE);
    EPWM_selectPeriodLoadEvent(EPWM5_BASE, EPWM_SHADOW_LOAD_MODE_SYNC);
    EPWM_setPhaseShift(EPWM5_BASE, phase_shift3);
    EPWM_setTimeBaseCounter(EPWM5_BASE, phase_shift3);

    EPWM_enablePhaseShiftLoad(EPWM6_BASE);
    EPWM_selectPeriodLoadEvent(EPWM6_BASE, EPWM_SHADOW_LOAD_MODE_SYNC);
    EPWM_setPhaseShift(EPWM6_BASE, phase_shift3);
    EPWM_setTimeBaseCounter(EPWM6_BASE, phase_shift3);

    // Synchronization
    EPWM_setSyncOutPulseMode(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO);
    EPWM_setSyncOutPulseMode(EPWM2_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);
    EPWM_setSyncOutPulseMode(EPWM3_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);

    SysCtl_setSyncInputConfig(SYSCTL_SYNC_IN_EPWM4, SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT);
    EPWM_setSyncOutPulseMode(EPWM4_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);
    EPWM_setSyncOutPulseMode(EPWM5_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);
    EPWM_setSyncOutPulseMode(EPWM6_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);

    // Enable sync and clock to PWM
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
}

over 1 year ago

+1 Ryan Ma over 1 year ago

TI__Mastermind 21696 points

Hi,

I looked at your code and the first thing I wanted to ask is are you syncing every counter == ZERO event when HR is enabled? This can cause jitter according to our TRM. Instead can you try to configure a sync out pulse only when you need to synchronize the PWMs? If this does not help, we can further look at what may be the issue.

It appears you're duty cycle follows the minimum duty cycle of 3 TBCLKs. For the MEP edge control on the case j%2!= 0, you are configuring the MEP edge control on the falling edge at TBCTR == 0. Instead could you set the MEP edge control to be on rising edge for when j % 2 != 0.

Please let me know if these changes help. Also could you provide a scope shot of the signal? Do you realize jitter on the outputs of both A/B?

Best,

Ryan Ma

0 user4913395 over 1 year ago in reply to Ryan Ma

Prodigy 10 points

Ryan Ma,

thank you, this solved the problem. Somewhere along the way I forgot that the MEP edge control takes place only after the action qualifier and consequently set the MEP edge control on falling edge for all the channels.

Best regards

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28379D: HRPWM issue