TMS320F280039C: How slow CLB clock can be?

Hello Wayne,

Wayne Huang said:

The user wonders how slow CLB clock can be for its 32-bit counter when SYSCLK = EPWM clock = 120MHz?

The CLB clock comes from the SYSCLK, so it can be as low as that frequency goes with respect to the ePWM (which according to the datasheet is 2 MHz). As long as the clock can be supplied, I believe the CLB should be able to count just fine (although the counter increments will represent longer durations in time).

Wayne Huang said:

From 32.2.1 CLB Clock of TRM, does it mean ASYNC is required in this case?

ASYNC is required when you need an asynchronous signal with respect to the rest of the device's clocking, you can use it if you want but as I stated above I think the SYSCLK does go pretty low (another expert can confirm if this is the case or not), although maybe not to 100 kHz.

Wayne Huang said:

What are AUXPLL and CLBCLKCTL.CLBCLKDIV? Are these part of CLB registers? How can the user set them in Sysconfig GUI?

It looks like the F28003x doesn't have it explicitly laid out in the datasheet clocking diagram, but this is basically where AUXPLL comes from:

I believe the CLBCLKDIV is in one of the System Control registers, but I can't seem to find it (the only other reference I see to it is the below table). I don't believe there's a way to configure them in SysConfig currently, but I will forward this to another expert to confirm.

Best regards,

Omer Amir

Dear Omer,

I am still confused.

When the user uses SYSCLK = EPWM clock = 120MHz (because they cannot slow down other parts including EPWM/CPU), what is the lowest speed for the 32-bit counter of CLB1 the user can set through register/Sysconfig to generate a very slow hardware-based PWM waveform by CLB counter?

That is, we want to confirm if and how to set the clock dividers inside CLB for the 32-bit counter if SYSCLK = EPWM clock = 120MHz.

Or it's required that CLB clock has to be same as SYSCLK = EPWM clock = 120MHz in this case?

Dear Omer,

Another question:

Since the user wants to output a very low-freq. PWM output by HW, is it possible to cascade two 32-bit counter where the output of the 1st counter is the input of the 2nd counter so that the total counter-length can be viewed as 64-bit?

In this case, the longest PWM can be

1/120MHz * (2^64)

That is, instead of using clock dividers to generate a slow clock, we are thinking to increase bit-length from 32-bit to 64-bit by cascading two counters to increase a PWM period.

Do you think it's feasible?

Wayne Huang said:

Since the user wants to output a very low-freq. PWM output by HW, is it possible to cascade two 32-bit counter where the output of the 1st counter is the input of the 2nd counter so that the total counter-length can be viewed as 64-bit?

Wayne Huang said:

Do you think it's feasible?

Yes, it is possible to cascade two counters in the CLB.