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TMS320F28388D: C2000Ware device.h support for INTOSC2 10MHz

Brad Caldwell
Genius 12595 points

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

We have a custom board and trying to get the ethernet stack up and running. Instead of supplying an external clock or XTAL, we're instead using INTOSC2 which defaults to 10MHz if I'm reading things correctly in the documentation. 

We found that in the device.h file

C:\ti\C2000Ware_5_00_00_00\device_support\f2838x\common\include\device.h

There's no option in the clock setup for 10MHz. All that's there is are definitions for 20MHz or 25MHz. Nothing for INTOSC2.

//*****************************************************************************
//
// Defines related to clock configuration
//
//*****************************************************************************
#ifdef USE_20MHZ_XTAL

...snip...

#else // USE_25MHZ_XTAL

...snip...

#endif

I need help defining the symbols for INTOSC2 10MHz.

Thank You

  • 0
    TI__Mastermind 44030 points

    Hi Brad,

    For applications requiring stringent clocking requirements like ethernet, CAN, CAN-FD the INTOSC accuracy (+/-3%) will not meet the timing requirements.  Anyway, to produce 200MHz SYSCLK from INTOSC2, use the following definitions:

    #define DEVICE_OSCSRC_FREQ          10000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 10MHz (INTOSC2) * 40 (IMULT) / (1 (REFDIV) * 2 (ODIV) * 1(SYSDIV))
//
#define DEVICE_SETCLOCK_CFG          (SYSCTL_OSCSRC_OSC2 | SYSCTL_IMULT(40) | \
                                      SYSCTL_REFDIV(1) | SYSCTL_ODIV(2) | \
                                      SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
                                      SYSCTL_DCC_BASE_1)

    This will produce a VCO clock of 400MHz and scaled down to produce 200MHz SYSCLK.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    TI__Mastermind 44030 points

    Hi Brad,

    Responding to the email thread from LM:

    However, his answer ommitted direction on the other #defines in that section:

    1. DEVICE_SYSCLK_FREQ – I can infer what’s needed here from what he directed about DEVICE_SETCLOCK_CFG.
    2. DEVICE_LSPCLK_FREQ – is this one unchanged (from DEVICE_SYSCLK_FREQ/4)?
    3. DEVICE_AUXSETECLOCK_CFG and DEVICE_AUXCLK_FREQ  -  unclear what to do  here; because my initial stab at DEVICE_SETCLOCK_CFG was incorrect based on Joseph’s direction, I suspect I also had this incorrect.

    Here are the defines for #1 and #2.

    #define DEVICE_SYSCLK_FREQ                 ((DEVICE_OSCSRC_FREQ * 40) / (1 * 2 * 1))

    #define DEVICE_LSPCLK_FREQ                 (DEVICE_SYSCLK_FREQ / 4)

    Auxilliary clock is an alternate clock source for other peripherals like USB and CAN that can be supplied on the auxilliary clock input which is different from X1.  If auxilliary clock is not required then DEVICE_AUXSETECLOCK_CFG and DEVICE_AUXCLK_FREQ can be ignored.

    Regards,

    Joseph