TMS320F280049C: IODFTCTRL register bit19:20(PINSAMPLEMASK) of the LIN module

Hi Yale,

Thanks for your question.

Yale Li 李耀先 said:

1. What does TBIT_CENTER represent and how to calculate SCLK?

I believe it is referring to the majority vote scheme falling edge shown in the image below:

SCLK is actually same as VCLK which in this device is same as SYSCLK frequency.

Yale Li 李耀先 said:

2. The TX sending value is flipped, how to ensure correct reception?

Do you mean just checking the data being received is correct? That should be readable in the receive buffer correct? I might be misunderstanding the question.

Yale Li 李耀先 said:

3. I set the value to 1, used loopback mode through the transmit pin, captured the signal with a logic analyzer, and found no flip. How to observe the function of this register?

This is not meant to be tested with loopback mode. It is meant to test reception from another device and observe on TX pin the bit flipping based on input data.

Regards,

Vince

Hi Yale,

Yale Li 李耀先 said:

The customer wants to know what changes will occur in the transmission or reception of the LIN module after setting this bit to 1 or 2 compared with when it is not set. Can you describe the process in detail? How to observe this change?

Maybe I am misunderstanding the question, but the register mentions what happens when this bit is set:

1. RX receives data

2. TX will toggle output level (high-low, and low-high) every time TBIT_CENTER is detected.

3. User can read the TX pin to see where within each bit the majority vote detection circuit is triggering the bit detection. This can be done with an oscilloscope for example.

Regards,

Vince