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TMS320F28377D: "Busy" bit not set to 1 after writing message number to bits [7:0] of the IF1 Command Register?

兆顺 邓
Prodigy 25 points
Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE

According to technical reference document, after writing message number to bits [7:0] of the IF1 Command Register, the transfer between the IF1/IF2 Register sets and the Message RAM will be initiated and the Busy bit is automatically set to '1'. However, it is not the case during my debug process, as the busy bit keeps to be 0 at the breakpoint right after setting the bits [7:0] of the IF1 Command Register. I also tried the C2000Ware example "can_ex4_simple_transmit" and got the same result. Why?

  • 0
    TI__Guru* 95315 points

    The TRM says the following: "With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in progress. After 4 to 14 clock cycles, the transfer between the Interface Register and the Message RAM will be completed and the Busy bit is cleared". Note that the busy bit could be cleared in as fast as 4 clock cycles. If you look at the disassembly window, it is conceivable that 4 cycles have elapsed when you check the status of the Busy bit. In other words, before you even get to checking the status of the busy bit, it has already been cleared.