Part Number: TMS320F280049C
HI
We are performing functional safety analysis of our electric system. The system’s brain where decision making and processing occurs is the TI microprocessor.
Reading through the documentation Functional TMS320F28004x Safety Manual UG (Rev. D), I can see that the microprocessor “independently assessed to meet a systematic capability compliance of ASIL D (according to ISO 26262:2018) and SIL 3 (according to IEC 61508:2010)”.
As we understand it, this capability level is contingent on implementing all the safety mechanisms (SM) listed by TI, to mitigate/design out/lower the occurrence of hazards.
For our application, the required capability is lower than ASIL D. We therefore would like to understand which SM are required to be implemented (i.e. what is needed to achieve PL/ASIL targets for the micro in isolation)
Could you share with us the FMEDA and any simulation tool (as mentioned in page 4 of the referenced document) that would allow us to determine the SM VS our required safety integrity levels for the microprocessor.
Best regards
