Dear Expert
I encountered a sampling issue while debugging with 280025 .
The blue represents the actual output voltage of my entire machine at 12.2V, while the green represents the time it takes for my program to raise the IO port when it detects that the actual output voltage is less than 12.10V,
There are over 100 us in the middle delay, and the hardware circuit sampling uses resistor voltage divider. May I ask what may be the reason for my software ADC configuration sampling?
Currently, the timer 100K is used for triggering, and the ADC configuration code is as follows. Please help analyze it. Thank you, there is no delay from the hardware signal to the DSP analog port.
static void sInitAdc(void)
{
//ADCA clock
EALLOW;
CpuSysRegs.PCLKCR13.bit.ADC_A
= 1;
// CpuSysRegs.PCLKCR13.bit.ADC_B = 1;
CpuSysRegs.PCLKCR13.bit.ADC_C = 1;
// Device_cal(); //bootrom会调用，这里是避免仿真时不执行bootrom
EDIS;
//ADC 参考电压3.3V
SetVREF(ADC_ADCA, ADC_INTERNAL, ADC_VREF3P3);
//SetVREF(ADC_ADCB, ADC_INTERNAL, ADC_VREF3P3);
SetVREF(ADC_ADCC, ADC_INTERNAL, ADC_VREF3P3);
DELAY_US(1000);
EALLOW;
AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;//转换结束产生事件
//3200W LLC
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 3;//temp AMB
AdcaRegs.ADCSOC1CTL.bit.CHSEL
= 1;
AdcaRegs.ADCSOC2CTL.bit.CHSEL
= 12;//temp SEC
AdcaRegs.ADCSOC3CTL.bit.CHSEL
= 2;
AdcaRegs.ADCSOC4CTL.bit.CHSEL
= 5;
AdcaRegs.ADCSOC5CTL.bit.CHSEL
= 4;//输出电流采样
AdcaRegs.ADCSOC6CTL.bit.CHSEL
= 15;
AdcaRegs.ADCSOC7CTL.bit.CHSEL
= 6;
AdcaRegs.ADCSOC8CTL.bit.CHSEL
= 3;//输出电压采样
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 9;//Sample window is 10 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC3CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC4CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC5CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC6CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC7CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC8CTL.bit.ACQPS = 9;
//tbd
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 2;//CpuTimer1 fs=100k
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 2;
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 2;
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 2;
AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = 2;
AdcaRegs.ADCSOC5CTL.bit.TRIGSEL = 2;
AdcaRegs.ADCSOC6CTL.bit.TRIGSEL = 2;
AdcaRegs.ADCSOC7CTL.bit.TRIGSEL = 2;
AdcaRegs.ADCSOC8CTL.bit.TRIGSEL = 2;
//tbd
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 8;// End of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 0;// Enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;// Make sure INT1 flag is cleared
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;//power up
EDIS;
//ADCB
EALLOW;
AdccRegs.ADCCTL2.bit.PRESCALE = 6;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;//转换结束产生事件
AdccRegs.ADCSOC0CTL.bit.CHSEL = 1;//ADDR2
AdccRegs.ADCSOC1CTL.bit.CHSEL = 4;//VFB
AdccRegs.ADCSOC2CTL.bit.CHSEL = 10;//IFB
AdccRegs.ADCSOC0CTL.bit.ACQPS = 9;//Sample window is 10 SYSCLK cycles
AdccRegs.ADCSOC1CTL.bit.ACQPS = 9;
AdccRegs.ADCSOC2CTL.bit.ACQPS = 9;
//tbd
AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 2;//CpuTimer1 fs=83k
AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 2;
AdccRegs.ADCSOC2CTL.bit.TRIGSEL = 2;
AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 2;// End of SOC2 will set INT1 flag
AdccRegs.ADCINTSEL1N2.bit.INT1E = 0;// Enable INT1 flag
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;// Make sure INT1 flag is cleared
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;//power up
EDIS;
DELAY_US(1000);
//PIE
//EALLOW; //diable
//PieVectTable.ADCA1_INT
= &ADCA1_ISR; //tbd
//EDIS;
//PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
//IER |= M_INT1;
}
