TMS320F280049: TIDM02002

yong luo said:

Will it not cause the state machine, ISR2, and ISR3 to not run (because the interrupt cycle is only 2us)?

ISR1 execution will preempt the operation of ISR2 and ISR3, but because of the time it takes to execute and the frequency at which it is ran this does not stop ISR2 and ISR3 from completing.

yong luo said:

In fact, when I run CLLLC code in the F28001137 environment, when I open the loop for 100K, the state machine, ISR2, and ISR3 do not run, and the entire program only runs ISR1

In open loop ISR1 may not run because it is only enabled when a change in key parameters are detected in ISR2. ISR2 and ISR3 should always execute regardless of code permeation.  

Regards,
Cody 

Taken from CLLLC.h

yong luo said:

key parameters are detected in ISR2? Can you provide more details?

No, the following understanding is incorrect.

yong luo said:

When the frequency of the open-loop PWM1 is set too high (e.g. 100K), due to the fast triggering of the ISR1 interrupt, ISR2 and ISR3 will not run (due to the interrupt sequence and priority), and the state machine will not run. Of course, this phenomenon also occurs during closed-loop control (because PWM1 controls the resonant upper and lower bridge arms)

This understanding is not correct as ISR does not operate every PWM cycle, as stated previously it is disabled and only enabled by ISR2. Therefore it only runs at the rate of ISR2. As you have noted ISR1 is synchronous to the Primary LEG1 PWM, but it does not execute every cycle.

yong luo said:

Because at CLLLC_ HAL_ In the setupInterrupt (CLLLC_powerFlowState Active. CLLLLC-PowerFlowState Enum) function, ISR1 is set to PWM1 interrupt. I think ISR1 will run continuously throughout the entire control, whether in an open loop or a closed loop;

The intention is to maintain good regulated control of a CLLLC DCDC stage.

yong luo said:

I don't understand what the design intention is?

There probably is an unused PWM, but that would not accomplish the goal. ISR1 updates all values related to the PWM for the system, it must do so synchronously to the CLLLC's operation. Shadow to active loads occur at a specific point in the PWM period so all values must be updated before that time, If they are not updated then the various PWMs may not be updated to the new values. This would cause the various PWMs to potentially operate at different frequencies, duty,  or phase shifts

yong luo said:

There is a fixed frequency PWM in the program that does not participate in controlling the bridge arm. I wonder if ISR1 can set a fixed frequency trigger so as not to affect the entire system control?