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TMS320F280039C: how can Watchdog clock time period is lower than that of INTOSC1 time period

Part Number: TMS320F280039C

Hello There,
I am Trying to configure Watchdog timer with INTOSC1 = 10Mhz. As stated in the Reference manual (snapshot attached below) "The watchdog reset or interrupt pulse is 512 INTOSC1 cycles long, so the counter period must be longer. To guarantee this, the product of the prescaler and pre-divider must be greater than or equal to four." thus I have set prescaler as 2 and pre-divider as 2 so that the product is 4 which is valid according to the above statement. By these calculations the watch dog count-time is calculated to be 0.4 microseconds and the INTOSC1(internal oscillator clock time period) is 51.2 microseconds. which should be invalid according to the above statement, please clarify this topic?

  • Tajas,

    thus I have set prescaler as 2 and pre-divider as 2 so that the product is 4 which is valid according to the above statement. By these calculations the watch dog count-time is calculated to be 0.4 microseconds

    There is 8bit counter which run off the divided clock so in this case watchdog count time would be 256 * 4 * 100 = 102.4 uS.

    Vivek Singh

  • There is 8bit counter which run off the divided clock so in this case watchdog count time would be 256 * 4 * 100 = 102.4 uS.

    Hello Vivek,

    can you specify from where did you find this equation to find watchdog count?

    also can you specify how watchdog count and reset pulse works with each other? I understood that for each watchdog countdown time it increment till 256 times and every reset pulse duration time perform reset operation. and how reset pulse is 2 times of countdown time?

    Regards,

    Mohit

  • Mohit,

    There is 8bit counter and when it overflows, reset/interrupt is asserted and it get stretched by 512 INTOSC1 clock. Please refer "Watchdog Timer Module" figure.

    Vivek Singh