Part Number: TMS320F280039C
Other Parts Discussed in Thread: SYSCONFIG
I'm Configuring Watchdog timer. Here,
INTOSC1 = 10MHz
INTOSC1(Time Period) = 0.1microsec
Prescaler = 2; Predivider = 2
Prescaled Time Period = 0.1*2*2 = 0.4 microsec.
Counter Period = 0.4 * 256 = 102.4 microsec.
(note: 8 bit counter so 2^8 = 256)
Now, according to the reference Manual "The watchdog reset or interrupt pulse is 512 INTOSC1 cycles long, so the counter period must be longer. To guarantee this, the product of the prescaler and pre-divider must be greater than or equal to four. The default prescaler value is 1."
We satisfy the condition of product of prescaler and predivider is 4.
While Configuring in Sysconfig When setting prescaler and predivider, the Reset pulse duration is double that of the watchdog countdown time. can you please clarify how is the watchdog reset pulse duration is twice, when it is stated that the counter period must be longer than that of the Reset pulse duration.
