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TMS320F28388D: ESC: How to set nMII_Link Polarity

ShawnYu
Intellectual 265 points

Part Number: TMS320F28388D

Hi, experts,

I found a description in TRM as shown in the figure below. It shows that the MII_Link signal has an additional polarity setting, but I didn't find any more information. Are there more detailed instructions on how to set this polarity and how it works?

Regards,

Shawn

  • 0
    Intellectual 265 points

    Also, I have a question about the register "ESCSS_CONFIG_REGS.ESCSS_PHY_IO_CONFIG.PHY_PORT_CNT". I tried to set it to 0 (one port operation) during ESCSS initialization, but found that both port0 and port1 still worked. I wrote the WRITE_KEY correctly when updating the register, and read back to find that PHY_PORT_CNT is indeed equal to 0.

    So I want to know what the actual function of this register is, and what are the precautions when setting it?

    Regards,

    Shawn

  • 0 in reply to ShawnYu
    TI__Mastermind 36526 points

    Shawn,

    Please allow me to get back to you about this tomorrow.

    Best Regards,

    Ben Collier

  • 0 in reply to Benjamin Collier
    Intellectual 265 points

    Hi, Ben,

    Is there any new progress on this issue?

    Regards,

    Shawn

  • 0 in reply to ShawnYu
    TI__Mastermind 36526 points

    Shawn,

    I apologize for the delay, I had to reach out to a designer about both of these issues, and I am waiting to hear back.

    Best Regards,

    Ben Collier

  • 0 in reply to Benjamin Collier
    Intellectual 265 points

    Thank you, Ben. Please let me know if there are any updates.

    My actual application requirements are as follows: In my system, port0 and port1 of the slave have normal physical layer connections. In some debugging situations, I need to close the slave port1 and loopback the data, but due to testing limitations, I can't do this by setting the DL control register or doing a loopback at the PHY level. Therefore, I hope to find a way to do some configuration ONLY at the salve ESC or DSP to turn off port1. Do you have any relevant suggestions?

    Regards,

    Shawn

  • +1 in reply to ShawnYu
    TI__Mastermind 36526 points

    Shawn,

    The designer has said that you can ignore the nMII_Link Polarity bit and gate since that bit will always be tied low internally. I am not sure why we document it in this diagram.

    Could you please take a look at the ESC DL Control register in the ESC registers? These are documented here:ethercat_esc_datasheet_sec2_registers_3i0.pdf

    Address in the TRM: 

    Best Regards,

    Ben Collier 

  • 0 in reply to Benjamin Collier
    Intellectual 265 points

    Hi,Ben,

    Thanks for your replay.

    1. Except for nMII_Link Polarity, could you please help me confirm the usage method of register "ESCSS_CONFIG_REGS.ESCSS_PHY_IO_CONFIG.PHY_PORT_CNT" I mentioned earlier?

    ShawnYu said:

    Also, I have a question about the register "ESCSS_CONFIG_REGS.ESCSS_PHY_IO_CONFIG.PHY_PORT_CNT". I tried to set it to 0 (one port operation) during ESCSS initialization, but found that both port0 and port1 still worked. I wrote the WRITE_KEY correctly when updating the register, and read back to find that PHY_PORT_CNT is indeed equal to 0.

    So I want to know what the actual function of this register is, and what are the precautions when setting it?

    2. I know the ESC DL  Control register, but this register is only allowed to be modified through the master. In my current tests, the master settings cannot be changed, so I am trying to find a way to close the port via the slave ESC or DSP, do you have any ideas? 

    Regards,

    Shawn

  • 0 in reply to ShawnYu
    TI__Mastermind 36526 points

    Hi Shawn,

    I apologize for the delays, but I do not think that I will be able to answer this question until the start of January since the designer is now out of office. 

    I am sorry that I could not get a clear answer for you before this.

    Best Regards,

    Ben Collier

  • 0 in reply to Benjamin Collier
    Intellectual 265 points

    Ok, looking forward to your reply. Please convey my test needs to designer to see if there are any good ideas or suggestions.

    ShawnYu said:
    2. I know the ESC DL  Control register, but this register is only allowed to be modified through the master. In my current tests, the master settings cannot be changed, so I am trying to find a way to close the port via the slave ESC or DSP, do you have any ideas? 

    Regards,

    Shawn

  • 0 in reply to ShawnYu
    TI__Mastermind 30185 points

    Hello Shawn,

    Ben is out-of-office until January 8th, please expect delays in replies until this time.

  • +1 in reply to ShawnYu
    TI__Mastermind 36526 points

    Shawn,

    After talking with our designer, it seems that the description for the ESCSS_CONFIG_REGS.ESCSS_PHY_IO_CONFIG.PHY_PORT_CNT bit was misleading, and there is no way to disable port1 with the ESCSS registers. If there is no way to do your tests while port1 is active, you will need to somehow disable the PHY. I'm not sure if this is achievable through software, but it may be possible by writing to the PHY registers through the MDIO interface.

    Best Regards,

    Ben Collier 

  • 0 in reply to Benjamin Collier
    Intellectual 265 points

    OK, I'll try some other way to make it. Thank you very much.