Hi,
the info on the sync delay was removed in chapter 20.4.3.3 Time-Base Counter Synchronization:
In previous TRMs you found:
The delay from internal control module to target modules is given by:
– if ( TBCLK = EPWMCLK): 2 x EPWMCLK
– if ( TBCLK < EPWMCLK): 1 x TBCLK
Why was this removed? What are the CLK delays?
Regards, Holger
