TMS320F2800137: CMPSS module

youjun zhang

Hi expert:

The functions of the comparator are as follows: when the input voltage（cmp0_hp） is greater than the set value (2V, using internal DAC), it outputs a high level，Output through XBAR-7

At present, the input voltage is 0v. When initializing CMPSS module, a high level of 30 ns will appear,why?

Did the comparator output become erratic during the internal DAC power on process after CMPSS_enablemodule?

over 2 years ago

0 Hadi Moradisizkoohi over 2 years ago

TI__Expert 7100 points

Hello Youjun,

Thanks for your patience.

As you can see in the figure, 4 different signal can be routed to the pins through OUTPUT X-BAR. Please let me know which signal your passing to OUTPUT X-Bar?

Regards,

Hadi

0 youjun zhang over 2 years ago in reply to Hadi Moradisizkoohi

Intellectual 610 points

output of digital filter device CTRIPOUTH passing to OUTPUT X-Bar?

And DACOUT = DACVALA*DACREF/4096.When cpmss enable,the DACOUT is start from 0?

what is the max time of the DAC power up?

0 Hadi Moradisizkoohi over 2 years ago in reply to youjun zhang

TI__Expert 7100 points

Youjun,

The recommended time for DAC power up is 500us. Also, there is a guideline for filter initialization given in section "12.5.1 Filter Initialization Sequence" in TRM.

Please note there is a errata related to latency to reset the COMPHLATCH path. You can find more information about that here.

Regards,

Hadi

0 youjun zhang over 2 years ago in reply to Hadi Moradisizkoohi

Intellectual 610 points

Question 1：The recommended time for DAC power up is 500us.Where can I find the data？

Question 2：When cpmss enable,the DACOUT is start from 0?

0 Hadi Moradisizkoohi over 2 years ago in reply to youjun zhang

TI__Expert 7100 points

Youjun,

Question 1:You can find it in section 6.12.5.5.1 CMPSS Comparator Electrical Characteristics.

Question 2: yes.

Regards,

Hadi

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TMS320F2800137: CMPSS module