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TMS320F28379D: ADC SOC Triggering Using epwm1

bandi Naga Chandra
Prodigy 140 points
Part Number: TMS320F28379D
Other Parts Discussed in Thread: SYSCONFIG, C2000WARE

Hello,

           In my application EPWM switching frequency = 50khz & ADC clock frequency is 50 MHZ, SYS clock = 200MHZ. once EPWM triggers the ADC, i want to sample each SOCS with sampling frequency of 250kHz (i..e sampling time is 4000ns). when i started configuring the SYSConfig tool it is taking sampling time max upto 2560ns. Is there any way to increase the sampling time using SYSCONFIG tool?

please refer the attachment. Any way to configure the ADCSOC's with required sample time?  

  • 0
    TI__Mastermind 38830 points

    Hi Bandi,

    What you have highlighted is ACQPS or acquisition time register.  This register determines the time that the sample and hold capacitor of the ADC closes in order to charge from the input signal being measured.  The capacitor charge is then processed by the ADC core in order to determine the digital value of the sampled signal.  This is not the same as sampling frequency.

    Sampling frequency is how often would the ADC be triggered to start a conversion.  In short, to vary the sampling frequency, the trigger signal events for SOC Trigger has to be varied.  For instance, in your code, it seems that you wanted to trigger conversion through EPWM counters.  To attain this, EPWM frequency has to be set to a multiple of the desired sampling frequency and counter compare register CMPA or CMPB.  See the C2000Ware example adc_ex2_soc_epwm.  In this example, the EPWM clock is set to 50MHz and the time base period is set to 1999 to attain a 25kHz sampling for ADC.  Tou can modify the same example to set the sampling frequency to your target of 250kHz.

    Regards,

    Joseph