TMS320F28069F: TMS320F28069F

Hello TI team,

We are using LAUNCHXL-F28069M for CAN implementation.

There is a problem, there no data on the can bus when we check the signal on the Oscilloscope.

Below is the code that i used for.

 Thanks

Nitish Sharma

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

//
// Function Prototypes
//
void mailbox_check(int32 T1, int32 T2, int32 T3);
void mailbox_read(int16 i);

//
// Globals
//
Uint32  ErrorCount;
Uint32  PassCount;
Uint32  MessageReceivedCount;

Uint32  TestMbox1 = 0;
Uint32  TestMbox2 = 0;
Uint32  TestMbox3 = 0;

//
// Main
//
void main(void)
{
    Uint16  j;

    //
    // eCAN control registers require read/write access using 32-bits.  Thus we
    // will create a set of shadow registers for this example.  These shadow
    // registers will be used to make sure the access is 32-bits and not 16.
    //
    struct ECAN_REGS ECanaShadow;

    //
    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the F2806x_SysCtrl.c file.
    //
    InitSysCtrl();

    //
    // Step 2. Initalize GPIO:
    // This example function is found in the F2806x_Gpio.c file and
    // illustrates how to set the GPIO to it's default state.
    //
    // InitGpio();  // Skipped for this example

    //
    // For this example, configure CAN pins using GPIO regs here
    // This function is found in F2806x_ECan.c
    //
    InitECanGpio();

    //
    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts
    //
    DINT;

    //
    // Initialize PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.
    // This function is found in the F2806x_PieCtrl.c file.
    //
    InitPieCtrl();

    //
    // Disable CPU interrupts and clear all CPU interrupt flags:
    //
    IER = 0x0000;
    IFR = 0x0000;

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in F2806x_DefaultIsr.c.
    // This function is found in F2806x_PieVect.c.
    //
    InitPieVectTable();

    //
    // Step 4. Initialize all the Device Peripherals:
    // This function is found in F2806x_InitPeripherals.c
    //
    // InitPeripherals(); // Not required for this example

    //
    // Step 5. User specific code, enable interrupts:
    //
    MessageReceivedCount = 0;
    ErrorCount = 0;
    PassCount = 0;

    InitECana();            // Initialize eCAN-A module

    //
    // Mailboxs can be written to 16-bits or 32-bits at a time
    // Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 15
    //
    ECanaMboxes.MBOX0.MSGID.all = 0x9555AAA0;

    //
    // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31
    //
    ECanaMboxes.MBOX16.MSGID.all = 0x9555AAA0;

    // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    //
    ECanaRegs.CANMD.all = 0xFFFF0000;

    //
    // Enable all Mailboxes
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    //
    ECanaRegs.CANME.all = 0xFFFFFFFF;

    //
    // Specify that 8 bits will be sent/received
    //
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;

    // Write to the mailbox RAM field of MBOX0 - 15
    //
    ECanaMboxes.MBOX0.MDL.all = 0x11111111;
    ECanaMboxes.MBOX0.MDH.all = 0xFFFFFFFF;

    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    //
    EALLOW;
    ECanaRegs.CANMIM.all = 0xFFFFFFFF;

    //
    // Configure the eCAN for self test mode
    // Enable the enhanced features of the eCAN.
    //
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.STM = 0;    // 1 for self-test mode, 0 for external
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
    EDIS;

    //
    // Begin transmitting
    //
    for(;;)
    {
        //
        // Set TRS for all transmit mailboxes
        //
        ECanaRegs.CANTRS.all = 0x0000FFFF;

        // Wait for all TAn bits to be set
        while(ECanaRegs.CANTA.all != 0x0000FFFF )
        {

        }

        ECanaRegs.CANTA.all = 0x0000FFFF;   // Clear all TAn
        for (int i=0; i<1000; i++);
    }
}

//
// mailbox_read - This function reads out the contents of the indicated
// by the Mailbox number (MBXnbr). MSGID of a rcv MBX is transmitted as the
// MDL data.
//
void
mailbox_read(int16 MBXnbr)
{
    volatile struct MBOX *Mailbox;
    Mailbox = &ECanaMboxes.MBOX0 + MBXnbr;
    TestMbox1 = Mailbox->MDL.all;   // = 0x9555AAAn (n is the MBX number)
    TestMbox2 = Mailbox->MDH.all;   // = 0x89ABCDEF (a constant)
    TestMbox3 = Mailbox->MSGID.all; // = 0x9555AAAn (n is the MBX number)
}

//
// mailbox_check -
//
void
mailbox_check(int32 T1, int32 T2, int32 T3)
{
    if((T1 != T3) || ( T2 != 0x89ABCDEF))
    {
        ErrorCount++;
    }
    else
    {
        PassCount++;
    }
}