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TMS320F280039: ORing of PWMs on a CLB with delay

Rhugved Rane
Prodigy 80 points
Part Number: TMS320F280039


I have two ePWM signals getting ORed on a CLB and the ORed signal is output on an IO pin
I want to introduce a delay in that ORed signal. How can this be done??

Detailed description:
We OR two ePWM signals using CLB,
And we output that ORed signal on an IO pin
This operation is almost instantaneous.

We want to introduce a delay in the ORed signal (a dead-band kind of thing)
This delay is in nano seconds
How can we achieve this thing in CLB??

  • 0
    TI__Mastermind 28220 points

    Hi Rhugved,

    Here's one way you could do this with the CLB:

    • Use a two-state FSM state as the output of your CLB.
    • Have two counters
    • The first counter will reset on the falling edge of your ORed PWM signal, while the second counter will reset on the rising edge of your ORed PWM signal.
    • Both counters will have the same counter match value that will correspond with your rising and falling edge delay.
    • Use the counter match events from both counters to toggle the state of the FSM.

    There is one limitation with this approach: If the time between two rising edges or two falling edges is ever less than your delay value, the counter will reset before the match event and the first rising/falling edge event will be ignored.

    Let me know if this is a suitable solution for your application.

    Thank you,

    Luke