TMS320F280049C: CLB clock config question

Hello,

Please note that our expert on this topic is currently out of office and expected to return on 8th Jan. Please expect a delay in response.

Regards,

Varsha

I have a question if this structure exist in 280049C:

How can I config the clock of CLB_register and CLB_tile to different frequency? I cannot find the config register mentioned in Table 29-1.

Apologies, it seems like I misspoke. I checked and this register is not available on the F28004x; I've updated the document so it should appear correct in the next release. This feature is part of type 3 CLB (see the C2000 Peripherals User's Guide for what CLB types apply to what devices).

The clock for the CLB is essentially controlled by only SYSCLK, which should have a maximum of 100 MHz.