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TMS320F280039: TMS320F280039

Amir Hussain
Expert 4175 points
Part Number: TMS320F280039


Hello

how to capture the counter value at the instant a DC event occurs?

I am working on a variable frequency control using an external ZCD signal. When a ZCD signal comes, I am generating the DC event. Using the digital compare sync event, I am making the counter (phase) of the EPWM 0. For the control purpose, I need to know the value of the counter before it goes to 0. Can you suggest how the capture the counter value? 

I tried using ECAP but I do not see any option of creating ECAP event using DC event.

Thank you

Amir Hussain

  • +1
    TI__Mastermind 26676 points

    Hi Amir,

    If you haven't looked at the DCCAPCTL register. This may help you capture the TBCTR when a DCEVTFILT signal occurs.

    To capture the counter value at the instant a DC event occurs, you can use the Digital Compare Capture Control Register (DCCAPCTL) in the Enhanced Pulse Width Modulator (ePWM) module. The DCCAPCTL register has a CAPMODE bit that, when set, captures the current Time-Base Counter (TBCNT) value in the active register when a Digital Compare Event Filtered (DCEVTFILT) occurs and the counter capture is enabled. Further trip (capture) events are ignored until the CAPSTS flag is cleared or until the next Period-equal (PRD_eq) or Counter-zero (CNT_zero) event re-triggers the capture mechanism, depending on the PULSESEL bit in the DCFCTL register.

    Here is the relevant information from the DCCAPCTL register description: - CAPMODE (Bit 15): Counter Capture Mode - CAPCLR (Bit 14): DC Capture Latched Status Clear Flag - CAPSTS (Bit 13): Latched Status Flag for Capture Event

    When a DC event occurs, the TBCNT value is captured in the active register. If the SHDWMODE bit is set, the active register value is copied to the shadow register on the PRD_eq or CNT_zero event. You can read the captured value from the CPU by accessing this register. 

    Looking at the available options, one method I would suggest is using an external interrupt generated from your external ZCD signal to trigger a DMA request.

    Note: There will be some delay from the external signal + the 3 * minimum TBCLK cycle for the digital compare signal to latch to the condition.

    With the external interrupt you can trigger the DMA to initiate the transfer the contents within the TBCTR to some memory location.

    Best,

    Ryan Ma