TMS320F280049C: Device Interconnect

Sorin,

What the safety manual is attempting to describe is the both the data/address bus connections from the CPU to peripherals(like the ADC or PWM or SPI) or memories, as well as any other logic that might be needed to arbitrate between multiple master accesses, for instance CPU and DMA access the same memory at the same time, that logic decided who goes first, etc.

So, if you aren't using the other bus masters, then the arbitration aspect of the 'interconnect" is not being used but the other components like muxes, the bus itself, and any kind of protocol converters would still be in use.

There isn't a standalone mechanism to test the interconnect itself; but you could use the DMA or CLA to access the same peripheral or memory and compare the value to the CPU used value, which would confirm the interconnect is working properly.  Depending on the criticality of that connection you choose to do this once at boot or periodically to check the integrity of the interconnect. 

An alternative, if there is some known/expected data in either a memory location or from a communication peripheral, being able to confirm that is what was read/received would also indicate the interconnect is good(along with the peripheral/memory/etc).

Best,
Matthew

Hi Matthew, Thanks for your reply. This makes sense.

Would the readback of the values stored in the peripheral, for example using the CPU would validate this though?

I don't want to add the DMA/CLA in the loop as then I would need to add diagnostics for them as well afterwards