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TMS320F28P650DK: TMS320F28P650DK9:EPWM event triggering error

lin huang
Prodigy 30 points

Part Number: TMS320F28P650DK

Hi TI Team,

         The EPWM cycle TB count value is configured as 12500, and the EPWM event trigger source is configured as either TB count to 0 or  period value. However, the TBCTR count for the  interruptions was 2188,7251,11732,58,12468,60,12467 How should this be handled?

The following is the EPWM configuration code：

EPWM_setClockPrescaler(EPWM1_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBasePeriod(EPWM1_BASE, (PwmPrdCountNum));
    EPWM_disablePhaseShiftLoad(EPWM1_BASE);
    EPWM_setPhaseShift(EPWM1_BASE, 0);
    EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_setTimeBaseCounter(EPWM1_BASE, 0U);
    EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, 0);
    // sync "down-stream"
    EPWM_enableSyncOutPulseSource(EPWM1_BASE,EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);
    EPWM_setCountModeAfterSync(EPWM1_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
    // Enable SOC-A and set it to assert when the counter hits
    // zero. It asserts on every event
    EPWM_disableADCTrigger(EPWM1_BASE, EPWM_SOC_A);
The following are the register values for the second interrupt entry
    EPWM_setADCTriggerSource(EPWM1_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);
    EPWM_setInterruptSource(EPWM1_BASE, EPWM_INT_TBCTR_ZERO|EPWM_INT_TBCTR_PERIOD);
    EPWM_setADCTriggerEventPrescale(EPWM1_BASE, EPWM_SOC_A, 1U);
    EPWM_enableADCTrigger(EPWM1_BASE, EPWM_SOC_A);
    // Enable Interrupt Generation from the PWM module
    EPWM_enableInterrupt(EPWM1_BASE);
    // This needs to be 1 for the INTFRC to work
    EPWM_setInterruptEventCount(EPWM1_BASE, 1U);
    // Clear ePWM Interrupt flag
    EPWM_clearEventTriggerInterruptFlag(EPWM1_BASE);

        Thanks & Regards

  • 0
    TI__Mastermind 28580 points

    Hi Lin,

    How are you reading your TBCTR value? I'm assuming you are doing this via an interrupt. Do you have any other interrupts in your system? This will affect the timing of when the EPWM interrupt begins. Even with no other interrupts, there is a large delay between when the event trigger condition occurs and when you'd enter into the ISR triggered by your event trigger, so you will not accurately be able to capture the counter value at the time of the event trigger via software.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 30 points

    HI Luke,

         EPWM1 will not be interrupted by other interrupts, and the TBCTR value recorded by the software should be close to the trigger value. The current phenomenon is that the time interval between the first three interrupts is significantly smaller than the cycle value, with the first time being 22.3us, the second time being 35us, and the third time being 50us. The period value is 62.5us, which means entering the interrupt earlier. After the third interruption, the cycle returns to normal.

  • 0 in reply to lin huang
    TI__Guru* 85620 points

    Lin,

    Just an update from our side, Luke is out today and Monday is US holiday.  Please expect our next reply Tuesday, the 16th of next week.

    Best,
    Matthew

  • 0 in reply to MatthewPate
    TI__Mastermind 28580 points

    Hi Lin,

    I suspect that your ISR is longer than your EPWM period. This would result in different TBCTR values being captured in each ISR since the beginning of each ISR would be delayed by the previous ISR. Could you verify that your ISR is shorter than your period by setting a GPIO high at the beginning of your ISR and setting it low at the end of your ISR? The resulting pulse should be shorter than your PWM period if you compare this GPIO output to your EPWM output.

    Thank you,

    Luke