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TMS320F280025C: CLB STOP Function

LIU LIU
Intellectual 390 points
Part Number: TMS320F280025C


In the TRM, CLB_LOAD_EN.STOP description as shown in below：

I want to know：

1. what behavior will the shown during debug HALTs of the CPU？

2. what is “sequential elements in the CELL” ？ 

  • 0
    TI__Mastermind 30185 points

    Hello,

    LIU LIU said:
    1. what behavior will the shown during debug HALTs of the CPU？

    If the STOP bit in the CLB_LOAD_EN is left at 0 (default on reset), then the CLB logic will continue to operate if signal inputs change.

    LIU LIU said:
    2. what is “sequential elements in the CELL” ？ 

    This is essentially the logic hardware in the CLB, i.e. the LUTs, FSMs, OUTLUTs, etc.

  • 0 in reply to Omer Amir
    Intellectual 390 points
    Omer Amir said:
    If the STOP bit in the CLB_LOAD_EN is left at 0 (default on reset), then the CLB logic will continue to operate if signal inputs change.

    1. What is "signal inputs change" means?

    2.Which is the behavior of CLB when STOP bit set to 1 and debug HALT of CPU coming？

    a. All sequential logic in CLB will halt like HLC, prescalar, counter, etc.

    b.CLB just cannot react to the outside input from other module from GLB_INPUT and LCL_INPUT. CLB internal sequential logic like HLC, prescalar, counter will continue to work 

    I cannot implement this function in 280025C. 

  • 0 in reply to LIU LIU
    TI__Mastermind 30185 points
    LIU LIU said:
    1. What is "signal inputs change" means?

    The CLB has 8 inputs, AKA boundary inputs. The signals which come in through these inputs may change which could result in changing the boundary outputs of the CLB which come from OUTLUTs.

    LIU LIU said:
    2.Which is the behavior of CLB when STOP bit set to 1 and debug HALT of CPU coming？

    The description you screenshotted states this implicitly, if set to 1 then the CLB's logic should not change while HALT'd.