TMDSCNCD28388D: How to generate a clock sequence with 23 clock pulses to read data from SSI (synchronous Serial Interface) Absolute optical encoder of 22 bit resolution

Hi,

If I understand the requirement, you would want to receive data from the encoder which works in SSI protocol.

For 23 bit data, you will have to use the SSI Datasize register(SSICR0.DSS) to configure it to the closest data size for the module to generate those many clocks.

I am not clear on your requirement with the clocks: you mean to ask, between each 23 clock pulse train(which is running at 100KHz) there has to be 30us of delay?

Regards,
Praveen

Hi, Thanks for ur reply.

Understanding is correct.  

Maximum data size of SSI Datasize register(SSICR0.DSS) is 16 bits only, please suggest to read remaining 6 bits from Encoder. 

30 Micro seconds gap is required between each clock pulse train to get updated value in the Encoder register, then with next clock pulse train it is possible read updated value.

In this Master is TMDSCNCD28388D board and slave is SSI encoder. Master sends clock pulse train to slave and slave sends data bits on every rising edge of the clock pulses to Master.

I have gone through SSI encoder questions in this forum, some of them are using existing SSI interface and some of them are using SPI interface. Please suggest which is most suitable interface to read 22 bits of information from SSI absolute optical single turn encoder.

For exact 22 bit read, you may have to split it as 16+6 by changing the DSS in between. The delay of 30us can be achieved by adding a software based delay in between these two transfers. Hope this takes care of your requirements.Please try this out and let us know.

In the meanwhile, I will also check internally with our encoder experts if there are better solutions for the same