Hello TI support team,
I'm writing to you since I need a confirmation about Crossbar.
Referring to the document SPRUIZ1A, I have looked into chapter 3 and paragraph 3.18 but I haven't found that Crossbar is connected to CPU1 only.
Please can you confirm my understanding or tell me how to connect Crossbar to CPU1 or CPU2 ?
Thank you very much,
Ettore
Hi Ettore,
By default all peripherals are controlled by CPU1, from my own investigation into the TRM, I could not find any CPUSEL bits or other registers for configuring XBARs to be controlled by CPU2:
All XBAR configuration should be done by CPU1, is there a requirement in your application to read or write to XBAR registers from CPU2? Read access may still be allowed for the XBAR flag registers for example.
Thank you,
Luke
