TMS320F28P659DK-Q1: Zero wait register, non-zero wait register, byte 0x80 aligned

Hi,

Yale Li 李耀先 said:

How should we understand the division of non-zero wait registers and zero wait registers mentioned in the BGCRC module? Are all ROM non-zero wait and RAM zero wait? Or is it based on timing? 

I don't think zero wait or non-zero wait matters for the BGCRC module. Also wait state depends on many aspects like multiple initiator access RAM or just one and for ROM it depends on the frq of operation. 

Yale Li 李耀先 said:

Why is the address aligned with 0x80?

That is just for ease of design.

Yale Li 李耀先 said:

Someone mentioned that BGCRC does not support access to Flash. Is it because Flash is too slow, so BGCRC is not used for checking?

Flash is timing critical interface and we did not want to add another read port to it hence flash access are not supported.

Regards,

Vivek Singh