This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28P650DK: CCS connecting problems

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: C2000WARE

Hi,
customer installed CCS12.6 and can't connect anymore. Following error message occurs:

His configuration:

Regards, Holger

  • Hi Holger,

    Please follow the steps to be able to connect to the device. I am using C2000WARE 5.01.00, with CCS12.6.

    1. Import the user defined target Config for TMS320F28P65x from C:\ti\c2000\C2000Ware_5_xx_xx_xx\device_support\f28p65x\common\targetConfigs\TMS320F28P650DK9.ccxml, you can use the one provided in the device support folder.

    2. Within this view, please uncheck and check back in the device TMS320F28P650DK9

    3. Click save

    4. Test Connection 

    5. Launch selected configuration

    6. Connect to Target

    7. Connected. Now you can load your .out file

    I am going to see why this does not simply work initially when importing the example from our SDK. Thank you for bringing this to our attention.

    Best,

    Ryan Ma

  • Hi Ryan,

    still not working.

    Regards, Holger

  • Hi Holger,

    I am using the latest CCS12.6 and not able to replicate this cache issue.

    Can you send me your target configuration? 

    Can you try using this latest target configuration? 

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/171/3750.TMS320F28P650DK9.ccxml

    Best,

    Ryan Ma

  • Hi Ryan,
    the .ccxml seem to be the same. In yours the CLA is CLA2 in CCS version it is CLA1.

    Regards, Holger

  • This is the latest target config provided by our software team. The version of CLA is Type2 for F28P65X.

    Let me know if this solves the issue or is the cache issue persisting? I would update the .ccxml with the one I provided, and restart CCS. Then test connection with the new target config.

    Best,

    Ryan Ma

  • Hi,
    it is not working with your target file. Attached it is the one he used. I think it is not the problem of the target file. Now he uninstalled CCS12.6 and installed CCS12.5 and it worked.

    Regards, Holger

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/171/TMS320F28P650DK9_5F00_old.ccxml

  • Hi Holger,

    I am unfortunately un able to replicate this exact issue on my side. What version of C2000WARE are you using?

  • Hi Ryan,
    I have an own EVM now and tried to run the example projects. They failed. Compilation was ok but load failed:

    [Active - CPU1_RAM]:

    C28xx_CPU1: GEL Output:
    Memory Map Initialization Complete
    C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
    C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
    C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after the selected CPU1/CPU2 flash banks executable are programmed.
    C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, and CPU2 Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 200MHz using INTOSC as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
    C28xx_CPU1: Before doing any flash operations using the flash plugin, (a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI. (b) Please select the flash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)
    C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
    C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
    C28xx_CPU1: File Loader: Verification failed: Values at address 0x00A80A@Program do not match Please verify target memory and memory map.
    C28xx_CPU1: GEL: File: C:\Users\a0406234\workspace_v12_6\gpio_ex2_toggle\CPU1_RAM\gpio_ex2_toggle.out: a data verification error occurred, file load failed.

    or [Active - CPU1_FLASH]:

    C28xx_CPU1: GEL Output:
    Memory Map Initialization Complete
    C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
    C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
    C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after the selected CPU1/CPU2 flash banks executable are programmed.
    C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, and CPU2 Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 200MHz using INTOSC as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
    C28xx_CPU1: Before doing any flash operations using the flash plugin, (a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI. (b) Please select the flash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)
    C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
    C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
    C28xx_CPU1: File Loader: Verification failed: Values at address 0x00A80E@Program do not match Please verify target memory and memory map.
    C28xx_CPU1: GEL: File: C:\Users\a0406234\workspace_v12_6\adc_ex1_soc_software\CPU1_RAM\adc_ex1_soc_software.out: a data verification error occurred, file load failed.

    CCS: 12.6
    C2000ware: 5.1
    I had to use XDS100 v2 (XDS110 is not working with the EVM).

    Regards, Holger

  • Hi Holger, 

    Which EVM are you using? ControlCard or Launchpad?

    This error mesage looks similar to this thread: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1319211/tms320f28p650dk-how-to-resolve-load-program-error

    Best,

    Ryan Ma

  • Hi Holger,

    Are you still having issues loading the .out file to the device?

    Can you attach your .ccxml so I can try and replicate your issue?

    Best,

    Ryan Ma