This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28P650DK: Trip zone force action: strange behavior

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: LAUNCHXL-F28P65X

Hello TI Support,
I'm using LAUNCHXL-F28P65X with a XF28P650DK9 and I'm facing with a strange behavior with the following bunch of instructions.
Let me describe the case: I put a breakpoint on the first Asm instruction and then I run the code step by step, till EDIS.


asm( nop);
EALLOW;
EPwm1Regs.TZFRC.bit.OST = 1;
EPwm9Regs.TZFRC.bit.OST = 1;
EPwm2Regs.TZFRC.bit.OST = 1;
EPwm10Regs.TZFRC.bit.OST = 1;
EDIS;


On EDIS, looking the flags OST register belonging to the Epwm modules, I mean,
EPwm1Regs.TZFLG.bit.OST
EPwm9Regs.TZFLG.bit.OST
EPwm2Regs.TZFLG.bit.OST
EPwm1Regs.TZFLG.bit.OST
I don't find all flags set to 1 as expected.


The goal of my "trip actions" is put the Epwm outputs to low level, so I have verified the "trip actions" through the oscilloscope.
I repeated the test many times and there is a delay among falling edges of Epwm outputs; falling because fields of TZCTL registers are set to "Force EPWM to low state".
The mentioned delay is bigger than half of switching period, 4us or bigger.

Let me say that I split this strange behavior into two parts:
first: CCS access register refresh
second: trip zone force by code

I can neglect the first topic but not the second one; so please can you help me ?

Thank you very much,

Ettore

  • Hi Ettore,

    Since you are using a software force to trip your PWM signals, I would expect there to be some delay between the timing of when each PWM gets tripped. However 4us seems very large, I would expect something in the tens of nanoseconds at worst.

    One approach you could take to have no delay between the PWMs getting tripped is to write to a GPIO output which is read by any of INPUTXBAR[1-3], and use the TZ[1-3] events to trip your PWMs. Let me know if this is a suitable approach. If not I can help investigate the cause of the 4us delay.

    Thank you,

    Luke

  • Hi Luke,

    thank you for your reply.

    Please let me dig my code, and in case I need your support I will back.

    In the meantime, may I leave the ticket open ?

  • Hi Ettore,

    Yes I will mark the ticket as "Waiting for Customer". It will reopen once you reply, however please respond with an update within 28 days or this thread may become locked.

    Thank you,

    Luke

  • Hi Luke, 

    I'm still digging for the strange behavior. 

    I have read the "Enhanced Pulse Width Modulator" chapter many times and it states that writing "1", through user code, on the OST field of the TZFRC register, the action immediately affects Pwm outputs. 

    However, based on what I see on my code, there is a delay among the action and the effect; the delay time is a random value, but always, it is as integer number of half interrupt period or 3.3us time quanta.

    Further, if I put a breakpoint on the code and I write the OST bit directly on Chip's register, through the Register Window I found on CCS, the flag OST on the TZFLG register doesn't rise even if I run the code step by step for a long. Please note that before this setting, I have set EALLOW on ST1.

    Based on this observation, it seems that the "setting of TZCTL" register, acts with as shadow register or something like that, but I haven't found it on the user manual.

    Does my story rise to you an idea about the issue ?

    PS: I have repeated some tests with an evaluation board with a TMS version of the chip, but the results didn't change.

    Thank you,

    Ettore

  • Hi Ettore,

    Could you try setting the FREE_SOFT bits in the TBCTL register to 11? It's possible the emulation mode for the PWM module is affecting the behavior of the TZFRC when the debugger is connected. If that doesn't have any affect I will test this issue on my side.

    Thank you,

    Luke

  • HI Luke

    sharing file offline

    thank you 

    BR
    Carlo

  • Hi Colombo,

    Our SME is currently OOO, expect responses to be delayed till next week.

    Best,

    Ryan Ma

  • Hi Carlo,

    I went through the file you sent via email. From your observations it seems the trip has a faster response time to an external trip compared to a software forced trip.

    Do you still wish to use the software forced trip for each of the EPWM modules, or are you planning on writing to a GPIO as an external trip source instead?

    Thank you,

    Luke

  • Hi Luke,

    what I want to do is:

    1) GPIO as an external trip source for entire ePWM modules allocated.

    2)  software forced trip for entire ePWM modules allocated.

    The case 1, is a typical switch off due to an electrical protection, while case 2 is related to a switch off by the code.

    For my application, case 2 must be as fast as case 1, and it must affect entire ePWM modules allocated.

    Thank you,

    Ettore

  • Hi Ettore,

    Understood. Do you have a spare GPIO you could use to implement case 2 so that the EPWM modules are all tripped simultaneously, or do you need to use the software forced trip? There will be an unavoidable delay between when the different EPWM modules are tripped if you trip them one by one in software. 

    Thank you,

    Luke

  • Hi Luke,

    thank you very much for your response.

    According to that, I will use a spare GPIO driven by software, that I will route inside through XBar module and then to the eWPM modules.

    Regards,

    Ettore