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TMS320F28388D: Integration of SIMULINK generated code project with EtherCAT SCC tool generated project in CCS

Mohamed Shaheen
Prodigy 50 points
Part Number: TMS320F28388D


Hello

I am in the process of integrating two projects in CCS.  The first project is bit-field code generated by SIMULINK embedded coder.  The second project is a DriverLib based project generated by EtherCAT SSC tool. All code is targeting CPU1.I followed the instructions in section 2.4 of the document "F2838x Firmware Development Package User's Guide".  The integrated code compiles and links without any issues but when deployed and run, TwinCAT is unable to scan the Device. When debugging I set some breakpoints and realized that HW_INIT() function is not succeeding and that the ESCSS memory initialization status check returns "ESC_HW_INIT_FAIL". I believe that the problem is that the bit-field code and the DriverLib based code are both setting clocks, GPIO's and interrupts. I commented out some of the lines in "ethercat_slave_cpu1_hal.c" to avoid conflicts. I am also using the link command file that is used by the bit-field code. It is worth noting that each of the projects works perfectly fine individually but the problem happens in the integrated code.

I am hoping that you can give me some advice to debug and fix the "ESC_HW_INIT_FAIL" issue. I am sharing the linker command file below.

Thanks,

-Mohamed

#include "MW_F2838x_MemoryMap.h"
#ifdef CLA_BLOCK_INCLUDED
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are. 
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_BLOCK_INCLUDED
MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
   BEGIN                    : origin = 0x000000,                length = 0x000002
   BEGIN_FLASH              : origin = 0x080000,                length = 0x000002
   #ifdef CLA_BLOCK_INCLUDED
        #if (CPU_RAMLS_PROG_LENGTH > 0)
            RAMLS_PROG      : origin = CPU_RAMLS_PROG_START,    length = CPU_RAMLS_PROG_LENGTH
        #endif //CPU_RAMLS_PROG_LENGTH
        RAMLS_CLA_PROG      : origin = CLA_RAMLS_PROG_START, 	length = CLA_RAMLS_PROG_LENGTH
        RAMLS_CLA_DATA      : origin = CLA_RAMLS_DATA_START, 	length = CLA_RAMLS_DATA_LENGTH
   #else
        #if BOOT_FROM_FLASH
            RAMLS_PROG      : origin = 0x008000, 				length = 0x002800
        #else
            RAMLS_PROG      : origin = 0x008000, 				length = 0x004000
        #endif //BOOT_FROM_FLASH
   #endif //CLA_BLOCK_INCLUDED
   
   #ifdef CPU1       
        #if (CPU1_RAMGS_PROG_LENGTH > 0)
            RAMGS_PROG      : origin = CPU1_RAMGS_PROG_START, 	length = CPU1_RAMGS_PROG_LENGTH
        #endif //(CPU1_RAMGS_PROG_LENGTH > 0)
   #else
        #if (CPU2_RAMGS_PROG_LENGTH > 0)
            RAMGS_PROG      : origin = CPU2_RAMGS_PROG_START, 	length = CPU2_RAMGS_PROG_LENGTH
       #endif //(CPU2_RAMGS_PROG_LENGTH > 0)
   #endif //CPU1

   /* Flash sectors */
   FLASHA_N                 : origin = 0x080002, 				length = 0x03FFFE	/* on-chip Flash */ 
   RESET                    : origin = 0x3FFFC0,                length = 0x000002
   
PAGE 1 :
   BOOT_RSVD           		: origin = 0x000002, 				length = 0x0001AE     /* Part of M0, BOOT rom will use this for stack */
   RAMM0M1                  : origin = 0x0001B0,                length = 0x000650
   RAMD0D1                  : origin = 0x00C000,                length = 0x001000
   
   #ifndef CLA_BLOCK_INCLUDED
        #if BOOT_FROM_FLASH
            RAMLS_DATA      : origin = 0x00A800, 				length = 0x001800
        #endif //BOOT_FROM_FLASH
   #endif //CLA_BLOCK_INCLUDED
   
   #ifdef CPU1       
        RAMGS_DATA       	: origin = CPU1_RAMGS_DATA_START, 	length = CPU1_RAMGS_DATA_LENGTH
   #else	
		RAMGS_DATA       	: origin = CPU2_RAMGS_DATA_START, 	length = CPU2_RAMGS_DATA_LENGTH
   #endif //CPU1
   
   #if defined(F28388D) || defined(F28386D) || defined(F28384D)
		RAMGS_IPCBuffCPU1        : origin = RAMGS_IPC_CPU1_START,          length = RAMGS_IPC_CPU1_LENGTH
		RAMGS_IPCBuffCPU2        : origin = RAMGS_IPC_CPU2_START,          length = RAMGS_IPC_CPU2_LENGTH
   #endif //#if defined(F28388D) || defined(F28386D) || defined(F28384D)
   
   CLA1_MSGRAMLOW           : origin = 0x001480,                length = 0x000080
   CLA1_MSGRAMHIGH          : origin = 0x001500,                length = 0x000080
   
   CPU1TOCPU2RAM            : origin = 0x03A000,                length = 0x000800
   CPU2TOCPU1RAM            : origin = 0x03B000,                length = 0x000800
   
   CPUTOCMRAM               : origin = 0x039000,                length = 0x000800
   CMTOCPURAM               : origin = 0x038000,                length = 0x000800
   
   CANA_MSG_RAM             : origin = 0x049000,                length = 0x000800
   CANB_MSG_RAM             : origin = 0x04B000,                length = 0x000800
   
   #ifdef EMIF1_CS0_INCLUDED
      EMIF1_CS0_MEMORY    : origin = 0x80000000,                length = 0x10000000
   #endif //EMIF1_CS0_INCLUDED
   #ifdef EMIF1_CS2_INCLUDED
      EMIF1_CS2_MEMORY    : origin = 0x00100000,                length = 0x00200000
   #endif //EMIF1_CS2_INCLUDED
   #ifdef EMIF1_CS3_INCLUDED
      EMIF1_CS3_MEMORY    : origin = 0x00300000, 				length = 0x00080000
   #endif //EMIF1_CS3_INCLUDED				
   #ifdef EMIF1_CS4_INCLUDED				
      EMIF1_CS4_MEMORY    : origin = 0x00380000, 				length = 0x00060000
   #endif //EMIF1_CS4_INCLUDED				
   #ifdef EMIF2_CS0_INCLUDED				
      EMIF2_CS0_MEMORY    : origin = 0x90000000, 				length = 0x10000000
   #endif //EMIF2_CS0_INCLUDED				
   #ifdef EMIF2_CS2_INCLUDED				
      EMIF2_CS2_MEMORY    : origin = 0x00002000, 				length = 0x00001000
   #endif //EMIF2_CS2_INCLUDED
}

SECTIONS
{
#if BOOT_FROM_FLASH
   /* Allocate program areas: */
   codestart                : > BEGIN_FLASH,              PAGE = 0,        ALIGN(8)
   .text                    : > FLASHA_N,                 PAGE = 0,        ALIGN(8)
   .cinit                   : > FLASHA_N,                 PAGE = 0,        ALIGN(8)
   .switch                  : > FLASHA_N,                 PAGE = 0,        ALIGN(8)
    #if defined(__TI_EABI__)
        .init_array         : > FLASHA_N,                 PAGE = 0,        ALIGN(8)
       /* Initalized sections go in Flash */
       .const               : > FLASHA_N,                 PAGE = 0,        ALIGN(8)
       .data                : > RAMGS_DATA,               PAGE = 1
       .TI.ramfunc          : {} LOAD = FLASHA_N,
                             #if CPU_RAMLS_PROG_LENGTH>0
                             RUN =  RAMLS_PROG,
                             #else
                             RUN = RAMGS_PROG,
                             #endif
                             LOAD_START(RamfuncsLoadStart),
                             LOAD_SIZE(RamfuncsLoadSize),
                             LOAD_END(RamfuncsLoadEnd),
                             RUN_START(RamfuncsRunStart),
                             RUN_SIZE(RamfuncsRunSize),
                             RUN_END(RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)

       ramfuncs          	: LOAD = FLASHA_N,
                             #if CPU_RAMLS_PROG_LENGTH>0
                             RUN =  RAMLS_PROG,
                             #else // Applicable when CLA BLOCK is included and CPULSRAM is zero
                             RUN = RAMGS_PROG,
                             #endif
                             LOAD_START(MW_RamfuncsLoadStart),
                             LOAD_SIZE(MW_RamfuncsLoadSize),
                             LOAD_END(MW_RamfuncsLoadEnd),
                             RUN_START(MW_RamfuncsRunStart),
                             RUN_SIZE(MW_RamfuncsRunSize),
                             RUN_END(MW_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
    #else
        .pinit              : > FLASHA_N,                 PAGE = 0,        ALIGN(8)
       /* Initalized sections go in Flash */
       .econst              : > FLASHA_N,                 PAGE = 0,        ALIGN(8)
       .TI.ramfunc          : {} LOAD = FLASHA_N,
                             #if CPU_RAMLS_PROG_LENGTH>0
                             RUN =  RAMLS_PROG,
                             #else // Applicable when CLA BLOCK is included and CPULSRAM is zero
                             RUN = RAMGS_PROG,
                             #endif
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)

        ramfuncs          	: LOAD = FLASHA_N,
                             #if CPU_RAMLS_PROG_LENGTH>0
                             RUN =  RAMLS_PROG,
                             #else // Applicable when CLA BLOCK is included and CPULSRAM is zero
                             RUN = RAMGS_PROG,
                             #endif
                             LOAD_START(_MW_RamfuncsLoadStart),
                             LOAD_SIZE(_MW_RamfuncsLoadSize),
                             LOAD_END(_MW_RamfuncsLoadEnd),
                             RUN_START(_MW_RamfuncsRunStart),
                             RUN_SIZE(_MW_RamfuncsRunSize),
                             RUN_END(_MW_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
    #endif // defined(__TI_EABI__)
    #ifdef CLA_BLOCK_INCLUDED
            #if defined(__TI_EABI__)
                /* CLA specific sections */
                Cla1Prog    : LOAD = FLASHA_N,
                              RUN = RAMLS_CLA_PROG,
                              LOAD_START(Cla1funcsLoadStart),
                              LOAD_END(Cla1funcsLoadEnd),
                              RUN_START(Cla1funcsRunStart),
                              LOAD_SIZE(Cla1funcsLoadSize),
                              PAGE = 0, ALIGN(8)
                .const_cla  : LOAD = FLASHA_N,
                              RUN = RAMLS_CLA_DATA,
                              RUN_START(Cla1ConstRunStart),
                              LOAD_START(Cla1ConstLoadStart),
                              LOAD_SIZE(Cla1ConstLoadSize),
                              PAGE = 0
                .bss        : > RAMGS_DATA,               PAGE = 1
                .bss:output : > RAMGS_DATA,               PAGE = 1
                .bss:cio    : > RAMGS_DATA,               PAGE = 1
            #else
                /* CLA specific sections */
                Cla1Prog    : LOAD = FLASHA_N,
                              RUN = RAMLS_CLA_PROG,
                              LOAD_START(_Cla1funcsLoadStart),
                              LOAD_END(_Cla1funcsLoadEnd),
                              RUN_START(_Cla1funcsRunStart),
                              LOAD_SIZE(_Cla1funcsLoadSize),
                              PAGE = 0, ALIGN(8)
                .const_cla	: LOAD = FLASHA_N,
                              RUN = RAMLS_CLA_DATA,
                              RUN_START(_Cla1ConstRunStart),
                              LOAD_START(_Cla1ConstLoadStart),
                              LOAD_SIZE(_Cla1ConstLoadSize),
                              PAGE = 0
                .ebss       : > RAMGS_DATA,               PAGE = 1
            #endif // defined(__TI_EABI__)
       #else
            #if defined(__TI_EABI__)
                .bss        : >> RAMGS_DATA | RAMLS_DATA, PAGE = 1
            #else
                .ebss       : >> RAMGS_DATA | RAMLS_DATA, PAGE = 1
            #endif // defined(__TI_EABI__)
       #endif //CLA_BLOCK_INCLUDED

   /* Allocate IQmath areas: */
   IQmath			        : > FLASHA_N,                 PAGE = 0,      ALIGN(8)  /* Math Code */
   IQmathTables		        : > FLASHA_N,                 PAGE = 0,      ALIGN(8)   
      
#else
   codestart        	    : > BEGIN,                    PAGE = 0
   .text                    : >> RAMLS_PROG | RAMGS_PROG, PAGE = 0
    #if (CPU1_RAMGS_PROG_LENGTH > 0)
      .cinit           	    : > RAMGS_PROG,               PAGE = 0
    #else
      .cinit           	    : > RAMLS_PROG,               PAGE = 0
    #endif
   .switch          	    : >> RAMLS_PROG  | RAMGS_PROG, PAGE = 0
   .TI.ramfunc              : >> RAMLS_PROG  | RAMGS_PROG, PAGE = 0
   ramfuncs         	    : >> RAMLS_PROG  | RAMGS_PROG, PAGE = 0
    #if defined(__TI_EABI__)
        .bss                : >  RAMGS_DATA,               PAGE = 1
        .bss:output         : >  RAMGS_DATA,               PAGE = 1
        .bss:cio            : >  RAMGS_DATA,               PAGE = 1
        .init_array         : >> RAMLS_PROG | RAMGS_PROG,  PAGE = 0
        .const              : >> RAMLS_PROG | RAMGS_PROG,  PAGE = 0
        .data               : >  RAMGS_DATA,               PAGE = 1
    #else
        .ebss               : >  RAMGS_DATA,               PAGE = 1
        .pinit              : >> RAMLS_PROG | RAMGS_PROG,  PAGE = 0
        .const              : >> RAMLS_PROG | RAMGS_PROG,  PAGE = 0
    #endif // defined(__TI_EABI__)
   /* Allocate IQ math areas: */
   IQmath				    : >> RAMLS_PROG | RAMGS_PROG,  PAGE = 0	/* Math Code */
   IQmathTables			    : >> RAMLS_PROG | RAMGS_PROG,  PAGE = 0
   #ifdef CLA_BLOCK_INCLUDED
       /* CLA specific sections */
       Cla1Prog             : > RAMLS_CLA_PROG,           PAGE = 0
       .const_cla           : > RAMLS_CLA_DATA,           PAGE = 0
   #endif //CLA_BLOCK_INCLUDED
#endif //BOOT_FROM_FLASH 
    #if defined(__TI_EABI__)
        .sysmem             : > RAMD0D1,                  PAGE = 1
    #else
       .esysmem             : > RAMD0D1,                  PAGE = 1
       .cio                 : > RAMGS_DATA,               PAGE = 1
    #endif // defined(__TI_EABI__)
   .stack                   : > RAMM0M1,                  PAGE = 1
   .reset                   : > RESET,                    PAGE = 0,      TYPE = DSECT /* not used, */
   MSGRAM_CPU1_TO_CPU2      : > CPU1TOCPU2RAM,            PAGE = 1
   MSGRAM_CPU2_TO_CPU1      : > CPU2TOCPU1RAM,            PAGE = 1
   MSGRAM_CPU_TO_CM         : > CPUTOCMRAM,               PAGE = 1
   MSGRAM_CM_TO_CPU         : > CMTOCPURAM,               PAGE = 1   
   #if defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED)
      .farbss               : > EMIF1_CS0_MEMORY | EMIF2_CS0_MEMORY,      PAGE = 1
      .farconst             : > EMIF1_CS0_MEMORY | EMIF2_CS0_MEMORY,      PAGE = 1
   #elif !defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED)
      .farbss               : > EMIF2_CS0_MEMORY,          PAGE = 1
      .farconst             : > EMIF2_CS0_MEMORY,          PAGE = 1
   #elif defined(EMIF1_CS0_INCLUDED) && !defined(EMIF2_CS0_INCLUDED)
      .farbss              : > EMIF1_CS0_MEMORY,          PAGE = 1
      .farconst            : > EMIF1_CS0_MEMORY,          PAGE = 1
   #else
      //No EMIF memory sections
   #endif //defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED)
   #ifdef EMIF1_CS0_INCLUDED
      Em1Cs0               : > EMIF1_CS0_MEMORY,          PAGE = 1
   #endif //EMIF1_CS0_INCLUDED
   #ifdef EMIF2_CS0_INCLUDED
       Em2Cs0              : > EMIF2_CS0_MEMORY,          PAGE = 1
   #endif //EMIF2_CS0_INCLUDED
   #ifdef EMIF1_CS2_INCLUDED
       Em1Cs2              : > EMIF1_CS2_MEMORY,          PAGE = 1
   #endif //EMIF1_CS2_INCLUDED
   #ifdef EMIF1_CS3_INCLUDED
       Em1Cs3              : > EMIF1_CS3_MEMORY,          PAGE = 1
   #endif //EMIF1_CS3_INCLUDED
   #ifdef EMIF1_CS4_INCLUDED
       Em1Cs4              : > EMIF1_CS4_MEMORY,          PAGE = 1
   #endif //EMIF1_CS4_INCLUDED
   #ifdef MW_EMIF2_CS2_INCLUDED
       Em2Cs2              : > EMIF2_CS2_MEMORY,          PAGE = 1
   #endif //MW_EMIF2_CS2_INCLUDED   
   #ifdef CLA_BLOCK_INCLUDED
       /* CLA C compiler sections */
       //
       // Must be allocated to memory the CLA has write access to
       //
       Cla1DataRam0		    : > RAMLS_CLA_DATA,           PAGE = 0

       Cla1ToCpuMsgRAM      : > CLA1_MSGRAMLOW, type=NOINIT               PAGE = 1
       CpuToCla1MsgRAM      : > CLA1_MSGRAMHIGH, type=NOINIT              PAGE = 1
       CLAscratch           :
                             { 
							     *.obj(CLAscratch)
							     . += CLA_SCRATCHPAD_SIZE;
							     *.obj(CLAscratch_end) 
						     } >  RAMLS_CLA_DATA,         PAGE = 0

       .scratchpad          : > RAMLS_CLA_DATA,           PAGE = 0
       .bss_cla		        : > RAMLS_CLA_DATA,           PAGE = 0
   #endif //CLA_BLOCK_INCLUDED

  #if defined(CPU1)  
       /* The following section definitions are required when using the IPC API Drivers */
            GROUP : > CPU1TOCPU2RAM,                      PAGE = 1
            {
                PUTBUFFER 
                PUTWRITEIDX 
                GETREADIDX 
                WRITEFLAG1CPU1
                WRITEFLAG2CPU1
                READFLAG1CPU1
                READFLAG2CPU1
            }
            GROUP : > CPU2TOCPU1RAM,                      PAGE = 1
            {
                GETBUFFER :     TYPE = DSECT
                GETWRITEIDX :   TYPE = DSECT
                PUTREADIDX :    TYPE = DSECT
                WRITEFLAG1CPU2 : TYPE = DSECT
                WRITEFLAG2CPU2 : TYPE = DSECT
                READFLAG1CPU2  : TYPE = DSECT
                READFLAG2CPU2  : TYPE = DSECT
            }
   #else
       /* The following section definitions are required when using the IPC API Drivers */ 
            GROUP : > CPU2TOCPU1RAM,                      PAGE = 1
            {
                PUTBUFFER 
                PUTWRITEIDX 
                GETREADIDX 
                WRITEFLAG1CPU2
                WRITEFLAG2CPU2
                READFLAG1CPU2			
                READFLAG2CPU2			
            }
            GROUP : > CPU1TOCPU2RAM,                      PAGE = 1
            {
                GETBUFFER :     TYPE = DSECT
                GETWRITEIDX :   TYPE = DSECT
                PUTREADIDX :    TYPE = DSECT
                WRITEFLAG1CPU1 : TYPE = DSECT
                WRITEFLAG2CPU1 : TYPE = DSECT
                READFLAG1CPU1  : TYPE = DSECT
                READFLAG2CPU1  : TYPE = DSECT
            }
   #endif //CPU1

    GROUP : > CPUTOCMRAM,                                 PAGE = 1
    {
        PUTBUFFERCPUX
        PUTWRITEIDXCPUX
        GETREADIDXCPUX
        WRITEFLAG1CPUX
        WRITEFLAG2CPUX
        READFLAG1CPUX
        READFLAG2CPUX
        VECTORDATA
    }
    GROUP : > CMTOCPURAM,                                 PAGE = 1
    {
        GETBUFFERCM :     TYPE = DSECT
        GETWRITEIDXCM :   TYPE = DSECT
        PUTREADIDXCM :    TYPE = DSECT
        WRITEFLAG1CM : TYPE = DSECT
        WRITEFLAG2CM : TYPE = DSECT
        READFLAG1CM  : TYPE = DSECT
        READFLAG2CM  : TYPE = DSECT
        VECTORDATA   : TYPE = DSECT
    } 

#if defined(F28388D) || defined(F28386D) || defined(F28384D)
	GROUP : > RAMGS_IPCBuffCPU1,                          PAGE = 1
	{
		CPU1TOCPU2GSRAM
	}
	GROUP : > RAMGS_IPCBuffCPU2,                          PAGE = 1
	{
		CPU2TOCPU1GSRAM
	}
#endif //#if defined(F28388D) || defined(F28386D) || defined(F28384D)
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

 

  • 0
    TI__Mastermind 36526 points

    Mohamed,

    From the way that you have described your problem, I would think that the GPIOs would be the cause of this issue. Can you setup your code so that the driverlib GPIO initialization is done after the bitfield? 

    As for the linker, are there major differences between the two? It is difficult for me to just look at one and find the issues.

    Best Regards,

    Ben Collier 

  • 0 in reply to Benjamin Collier
    Prodigy 50 points

    Ben,

    Thank you for the prompt response.  I do have the bit-field code initialization before the DriverLib code intialization. In fact, I was able to get the code to work yesterday with TwinCAT being able to scan and detect the device.  Earlier, I had commented out the following two lines in the "ethercat_slave_cpu1_hal.c":

    Device_enableAllPeripherals(); 
    Device_initGPIO();

    I un-commented the first one and kept the second commented out. This change enabled the EtherCAT GPIO configuration to be applied.

    In my bit-field code, I have ePWM1 and ePWM2 configured to use GPIO0, GPIO1, GPIO2 and GPIO3 for ePWM1A, ePWM1B, ePWM2A and ePWM2B respectively.  I configured trip zone TZ1 to turn ePWM1 and ePWM2 On/Off.  I use EtherCAT process data to change the "cmd" input to the function below:

     

    void hc_inverter_cmd(unsigned short cmd)
{
    #ifdef MATLAB_MEX_FILE
    #else
    static unsigned short inverter_state = 0U;
    if(inverter_state != cmd)
    {
        if(cmd == 1)
        {
            EALLOW;
            EPwm1Regs.TZCLR.all = 0x0004;
            EPwm2Regs.TZCLR.all = 0x0004;
            EDIS;
        }
        else
        {
            EALLOW;
            EPwm1Regs.TZFRC.all = 0x0004;
            EPwm2Regs.TZFRC.all = 0x0004;
            EDIS;
        }
    }
    inverter_state = cmd;
    #endif
}

    I monitor ePWM1A, 1B, 2A and 2B on the scope as I toggle the "cmd" value using TwinCAT.  ePWM1 channels have the correct response but the channels on ePWM2 are not responding. Not sure if this is a GPIO problem?

    Thanks,

    -Mohamed

       

  • +1 in reply to Mohamed Shaheen
    Prodigy 50 points

    Hello Ben,

    I resolved the issue with ePWM2 signals. Thanks for your help.

    Best regards,

    -Mohamed