Part Number: TMS320F28388D
Hello,
I'm new to the TMS320F28388D and more generally to the IPC.
I used the example of ipc_ex2_msgqueue_cm and ipc_ex2_msgqueue_c28x1. which I then adapted to my code, which must share data structures between these two processors.
What I want to achieve is that the CPU1 sends 3 data structures every 10ms to the CM, while the CM sends setpoint data asynchronously to the CPU1, or following a response to the status of one of the data structures received from the CPU1.
For each of the microprocessor, messages are received by interruption.
Everything works correctly in the CPU1 to CM direction, the 3 messages are received by IT every 10ms, and the data is correctly transferred to the CM memories.
On the other hand, in the CM to CPU1 direction, the CPU1 only receives the interrupt once, and therefore only once the data from the CM.
I don't understand what's going on, it's as if CPU1 blocked the IT after the first one. However, it leaves the interrupt after reading the data correctly and sending the ACK to the CM.
when I compare the IPC registers I don't see anything wrong:
Register status after transmission of the first CM message and before CPU1 acknowledgement:
Status IPC registers, CPU1 :
CMTOCPU1IPCSTS=1 (Flag0)
Status IPC registers, CM:
CMTOCPU1IPCFLG=1 (Flag0)
Once the ACK has been returned by CPU1, all IPC registers (both CPU1's IPCSTS and CM's IPCFLAG) are reset to 0.
On the other hand, the second time CM is sent, both registers, CMTOCPU1IPCFLG and CMTOCPU1IPCSTS, are reactivated, but CMTOCPU1IPCSTS apparently no longer causes an interrupt on CPU1?
Status of system registers during testing :
and:
These registers don't change at any stage, CM transmit, CPU1 recept..
To be sure it's not a problem of conflict between CPU1 and CM emissions, I made the last tests without CPU1 emitting anything.
The IPC interrption on CPU1 is the only one programmed.
The tests were carried out on the M063B evaluation board with CCS v12.5.0.00007.
Can you help me?
Thanks in advance.
Best Regards,
Eric
