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TMS320F28388D: Blocking Behavior of CPU2 and CPU2_CLA1 Accessing LSRAM

Wilko Moritz
Intellectual 265 points

Part Number: TMS320F28388D

Hello,

I am currently working with the TMS320F28388D microcontroller and exploring the functionality of the Local Shared RAM (LSRAM).

I am interested in understanding how blocking works when both CPU2 and CPU2_CLA1 of the microcontroller access the LSRAM.

Specifically, I would like to know if there are no blockage or conflict issues when CPU2 accesses LSRAM 01 while CLA1 simultaneously accesses LSRAM 02, for example.

If the above mentioned is true, I would further like to know if the blocking of the LSRAM affects the whole LSRAM or only the variable that the controller is writing on?

P.S. The information about the memory can be found in the TMS320F28388D Technical Reference Manual (TRM) in Chapter 3.12.

Regards,

Wilko

  • 0
    TI__Mastermind 30185 points

    Hello Wilko,

    Wilko Moritz said:

    I am interested in understanding how blocking works when both CPU2 and CPU2_CLA1 of the microcontroller access the LSRAM.

    Specifically, I would like to know if there are no blockage or conflict issues when CPU2 accesses LSRAM 01 while CLA1 simultaneously accesses LSRAM 02, for example.

    If you're talking about access arbitration, this is described in section 3.12.1.7 Access Arbitration of the device reference manual. Blocking specifically is controlled by access protection, which determines which controller has access to the RAM in general (i.e. not a per-write/read operation).

    There will be no conflicts based on the above arbitration scheme when two writes are issued to the same RAM (in the worst case, a read will return stale data).

    Wilko Moritz said:
    If the above mentioned is true, I would further like to know if the blocking of the LSRAM affects the whole LSRAM or only the variable that the controller is writing on?

    The arbitration/protection is per RAM, not per address.

  • 0 in reply to Omer Amir
    Intellectual 265 points

    Hello Omer,

    Thank you for the swift response. The clarification in your second part has already shed light on some uncertainties.

    To provide more context for the first part of my question, let me explain the scenario where my inquiry was focused:

    I have an interrupt running on my CLA with a very narrow timing window due to its frequent invocation. Currently, I am using a struct in the LSRAM to store all the relevant variables for this interrupt.

    Upon observing the timing of this interrupt, particularly by monitoring GPIO Set and GPIO CLEAR signals on an oscilloscope, I noticed instances where the interrupt takes longer than usual, especially when my CLA attempts to write to this struct.

    This led me to the conclusion that the delay might be caused by my CPU potentially blocking the LSRAM during its writes to this struct.

    My idea to mitigate this issue was to split the struct into two parts:

    • The first part would reside in LSRAM1, with the CPU being the sole writer while the CLA would have only read access.
    • The second part would reside in LSRAM2, with the CLA being the exclusive writer while the CPU would only read the data.

    Hence, my question was aimed at understanding if there exists independent Access Arbitration for LSRAM1 and LSRAM2.

    Furthermore, considering your earlier point that read access also undergoes access arbitration, I am curious to know if the read access is faster than write access. If not, there might be little gained from this endeavor.

    I hope this additional information provides a clearer picture of my inquiry.

    Regards, 

    Wilko

  • +1 in reply to Wilko Moritz
    TI__Mastermind 30185 points

    Hello Wilko,

    Wilko Moritz said:
    Hence, my question was aimed at understanding if there exists independent Access Arbitration for LSRAM1 and LSRAM2.

    Yes, these two RAMs have separate access arbitration, the access arbitration is for each RAM not all RAM as a whole. If you treat each RAM as separate, then you should have no problem accessing the memory in the way you've described.

    Wilko Moritz said:
    Furthermore, considering your earlier point that read access also undergoes access arbitration, I am curious to know if the read access is faster than write access.

    Per the RAM Specifications section in the datasheet, read time is longer than store time: