TMS320F280049C: configuring interrupts

Johnny Chen

Part Number: TMS320F280049C

Hi Champ,

I am asking for my customer.

As TRM section 3.5.4.3, it tells the procedures of disabling interrupts.

It specifies Enable interrupts globally (EINT or CLRC INTM) in step 6 after clearing all the IER/IFR in PIE stage and CPU stage in previous step 2~5.

(1). Why it is needed to additionally Enable interrupts globally in the end for disabling interrupts ? In my understanding, as soon as the step 2~5 are done, it should disable the peripheral's interrupt request propagating to CPU, correct ? Is the step 6 a must need to do or a suggestion to do ?

(2). If step 6 isn't done by user for disabling interrupts, what problem would it cause when we try to re-enable interrupts as the procedure specified in section 3.5.4.1 Enabling Interrupts following ?

Thanks and regards,

Johnny

over 1 year ago

0 Hareesh Janakiraman over 1 year ago

TI__Guru* 95315 points

Johnny,

I checked with a device architecture expert and got the following feedback:

"This note is explaining a code sequence on how to specifically disable one specific interrupt in the PIE. The assumption being that currently interrupts are enabled and you want to specifically turn OFF one particular PIE interrupt".

0 Johnny Chen over 1 year ago in reply to Hareesh Janakiraman

TI__Expert 5090 points

Hi Hareesh,

Thanks for the reply.

According to what you said, that means if there is only "one" interrupt request in the PIE, it should be no issue with or without doing Enable interrupts globally (EINT) to disable this interrupt, right ?

Thanks and regards,

Johnny

+1 Hareesh Janakiraman over 1 year ago in reply to Johnny Chen

TI__Guru* 95315 points

Johnny,

The procedure outlined in the TRM is to enable or disable one interrupt.

Johnny Chen said:
if there is only "one" interrupt request in the PIE, it should be no issue with or without doing Enable interrupts globally (EINT) to disable this interrupt, right ?

True.

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TMS320F280049C: configuring interrupts