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TMS320F28335: TMS320F28335

Part Number: TMS320F28335
Other Parts Discussed in Thread: C2000WARE, SYSCONFIG

Hello:

I encountered such a problem when configuring HRPWM with the TMS320F28335 series chip. The configuration code is as follows:

void
HRPWM6_Config(period)
{
//
// ePWM6 register configuration with HRPWM
// ePWM6A toggle high/low with MEP control on falling edge
//
EPwm6Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
EPwm6Regs.TBPRD = period-1;
EPwm6Regs.CMPA.half.CMPA = 0;// set duty control only by CMPAHR
EPwm6Regs.CMPA.half.CMPAHR = (255<< 8); // initialize HRPWM extension
EPwm6Regs.TBPHS.all = 0;
EPwm6Regs.TBCTR = 0;

EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;//count down mode
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM6 is the Master
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm6Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle high/low
EPwm6Regs.AQCTLA.bit.CAD = AQ_SET;
//EPwm6Regs.AQCTLB.bit.PRD = AQ_CLEAR;
//EPwm6Regs.AQCTLB.bit.CBU = AQ_CLEAR;

EALLOW;
EPwm6Regs.HRCNFG.all = 0x0;
EPwm6Regs.HRCNFG.bit.EDGMODE = HR_REP; // MEP control on raising edge
EPwm6Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm6Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
EDIS;
}

In the main function, I configure SYSCLKOUT=150MHz and TBCLK=150MHz, and pass 100 as the period parameter into the HRPWM6_Config(period) function, so the generated PWM frequency is 1.5MHz. Now the duty cycle is required to be 30.2%. When the high resolution edge is set as the falling edge, the PWM output is set up when CNT=ZRO, and the values of CMPA and CMPAHR are calculated according to the formula:

Assuming that the MEP step is 150ps, it corresponds to the SYSCLK frequency of 150MHz, and the corresponding MEPScaleFactor=44.44

The CMPA=integer(100*30.2%)=30;

The CMPAHR=(fraction(100*30.2%)*(MEPScaleFactor)+0.5(rounding))<<8=(0.2*44.44+0.5)<<8=2403;

Finally, according to the obtained CMPA and CMPAHR values, the PWM waveform with a duty cycle of about 30.2% can be obtained.

However, when configured with high resolution rising edge regulation, when CNT reaches the CMPA value calculated according to the above formula, after MEP edge control regulation, the PWM waveform is set up, and when CNT=PRD, the waveform is cleared to zero, then the obtained PWM waveform duty ratio is still 30.2% as required?

According to the above results, I think the obtained PWM waveform duty cycle should be 1-30.2=69.8%, rather than the required 30.2%, and if you want to obtain the required 30.2% duty cycle, in the rising edge control should be calculated according to 60.8% CMPA and CMPAHR values, or will the hardware help automatically switch? Or should we switch the value of duty cycle according to what I said, and then recalculate the value required by CMPA and CMPAHR according to the above formula?

Best Regards,

Runhao

  • Hi Runhao,

    Are you utilizing any C2000ware examples for this application?

    Also, are you using SFO library to calculate MEP steps? If so, are you using autoconversion? This will automatically calculate what is needed for HR based on the MEP step calculations and simplify them for you.

    Best Regards,

    Allison

  • Hi Allison,

    Although I used the example in C2000 and used the automatic calculation of the SFO library's MEP_ScaleFactor and turned on the automatic conversion, my current question is, do I need to deal with the 30.2 duty cycle separately when adjusting the rising edge and the falling edge?

    For example, I first set and clear CNT=ZRO and CNT=CAU using the falling edge adjustment in the up count mode:the waveform I get is shown in the first line,However, if I do not change the value of CAU, but only change the use of rising edge adjustment, and set it up when CNT=CAU, and clear it when CNT=PRD, then the waveform I get should be the PWM wave with a duty cycle of 69.8% as shown in the second line of the figure below.

    Therefore, my doubt is, if I want to obtain a 30.2% PWM waveform, should I modify the CMPA and CMPAHR values to 69.8% corresponding values when adjusting the rising edge, and obtain a PWM waveform with a 30.2% duty cycle as shown in the third row of the figure below? Or if SFO and automatic conversion are enabled, do you not have to consider this situation?

  • Hi Allison,

    I also specially used oscilloscope to verify the above behavior, as shown in the following figure:

    When I use the falling edge adjustment and set and clear CNT=ZRO and CNT=CAU and the duty cycle is set to 30.9%, the resulting waveform looks like this,

    When I do not modify the values set by CMPA and CMPAHR, I still modify AQ as set by 30.9%, set it up when CNT=CAU, clear it when CNT=ZRO, and adjust it with rising edge. The resulting PWM waveform is shown in the figure below.

    It can be seen from the measurement results of the oscilloscope that although I set the CMPA and CMPAHR according to 30.9%, the duty cycle of the actual output waveform is 69.1%.

    If I configure the values of CMPA and CMPAHR according to the duty cycle of 69.1%, the waveform obtained under the rising edge adjustment is shown in the figure below.

  • Hi Runhao,

    Thanks for the diagram and scope images. 

    If auto-conversion feature of HRPWM module is enabled then you can directly program all the 32-bits of CMPA register (both CMPA and CMPAHR) in one go. Once you set this HRCNFG[AUTOCONV] bit, you should also be able to write to the CMPAHR register from 0 to 0xFFFF and see a linear response throughout the range.

    Regarding the CMPAHR register, only the upper 8-bits contain the high-resolution portion (most significant 8-bits) as seen in the register description in the device TRM. And if auto-conversion mode is as enabled as I mentioned then the CMPAHR just needs to be populated with fractional duty and the hardware will automatically translate this into number of MEP steps with the help of SFO based calibration. 

    In regard to your latest oscilloscope captures, the first 2 cases look as I would expect- i.e. if you are changing your action qualifiers from {set on zero, clear on CMPA} to {set on CMPA, clear on PRD} without changing any other parameters, then I would expect the duty to be the inverse (30.9 for one configuration vs. 69.1 for the other). Keep in mind HR is always a delay element, and CMPAHR specifically applies delay to channel A according to what MEP edge control you have.

    Could you elaborate on the significance of the 3rd scope capture? Apologies if perhaps I am misunderstanding the question.

    Best Regards,

    Allison

  • Hi Allison,

    Thank you for your detailed explanation,For the third case, again based on {set CMPA,reset PRD}, I want to use the rising edge to adjust a PWM waveform with a duty cycle of 30.9%, but if the value in my CMPA:CMPAHR register is still calculated according to 30.9%, I will get a PWM waveform like the second case. Even if I turn on automatic conversion, I configure the CMPAHR register with a value of (0.9) <<8, and then the resulting PWM waveform is the same as in the second case.

    Therefore, in the third case, not only {set CMPA,reset CMPAHR} is used, but also the value of {CMPA:CMPAHR} is calculated according to the value of (1-30.9%) =69.1%, so that the PWM waveform is like the third case. A PWM waveform with a duty cycle of 30.9% is obtained by adjusting the rising edge.

    You can also pay attention to the first picture and the third picture on the far right where there is a ▲x parameter, indicating the time occupied by the high level, both are basically around 200ns, for 1.5MHz PWM waveform, the duty ratio can reach 29.999999% (error from the measurement), the visual difference between the two pictures is because of the oscilloscope scaling.

    Best Regards,

    Runhao

  • Hi Allison,

    Now I have a new problem about the regulation of high-precision period. From the description in the highlighted part of the following document, it can be seen that when the high-precision period register TBPRDHR is selected to regulate MEP, the duty ratio and phase can be adjusted separately, but the EDGMMODE can only select RE, and FE corresponds to the duty ratio adjustment. BE corresponds to phase adjustment, how can I adjust the period, duty cycle and phase at the same time?

    That is, can the high-resolution period, duty cycle, and phase be adjusted at the same time?

    Or can the high resolution period and resolution be adjusted at the same time?

    If it is possible, for example, if I select RE as the high resolution period, that is, the EDGMODE register bit has been determined, then my AQ should be set when CNT=PRD, then my duty cycle can only be adjusted with the falling edge, but my EDGMODE is chosen at RE.

    I am confused about these questions, please reply to me as soon as possible

    Best Regards,

    Runhao

  • Hi Runhao,

    Thanks for the explanation. Let me first try to understand/address the initial confusion:

    Case 1:

    • MEP edge control of rising edge
    • Action Qualifiers: 
      • Set high on CMPA-up
      • Clear low on PRD
    • Outcome:
      • If you are using CMPAHR, the delay elements will be applied to the rising edge
        • Hence, this will delay the edge that is on CMPA
      • From your calculations and diagrams, my understanding is this should result in 69.8% duty
      • If you instead wanted 30.2% duty, you should change you AQs or adjust your CMPA value accordingly

    Case 2:

    • MEP edge control of falling edge:
    • Action Qualifiers: 
      • Set high on ZERO
      • Clear low on CMPA-up
    • Outcome:
      • If you are using CMPAHR, the delay elements will be applied to the falling edge
        • Hence, this will delay the edge that is on CMPA
      • From your calculations and diagrams, my understanding is this should result 30.2% duty 

    In regards to your second post: 

    You can control both duty and phase with high resolution at the same time. Note that HR period control would just result in duty control since you're just adjusting the length of your PWM cycle with high resolution. You can use CMPxHR and TBPRDHR individually or use them together. However, you cannot use either of these in with TBPHSHR. So you essentially have two choices in deciding what parameters you want to control the MEP edge for PWM channels A and B:

    1. CMPAHR/CMPBHR or TBPRDHR
    2. TBPHSHR

    Note that there are some restrictions depending on which of the above you choose and also what count mode you choose. The recommended form of HRPWM signal is using up-down count mode with the PWM signal centered on PRD (meaning, you have action qualifiers on to set high CMPAU and clear low on CMPAD).

    If counter mode is up count mode and if HR mode is enabled:

    • Action qualifier settings need to be:
      • Set high on PRD
      • Clear low on CMPAU

    If you are using High Resolution Period mode (TBPRDHR):

    • MEP should control both edges
      • (both-edge-control is not supported in up-count mode, so you should use up-down count)
    • Auto-conversion must always be enabled for high resolution period mode (autoconversion is also called Automatic HRMSTEP Scaling)
    • CMPA must have shadow loading enabled and configured as:
      • Shadow load CMPA on TBCTR=PRD for up-count
      • Shadow load CMPA on TBCTR=0 or PRD for up-down count
    • CMPAHR must have shadow loading enabled and configured as:
      • Show load on CMPAHR on TBCTR=0 or PRD 

    Let me know if you need further clarification. Note that using the SysConfig GUI will catch most errors/incompatible HRPWM settings as well - this can be very helpful for your development.

    Best Regards,

    Allison

  • Hi Allison,

    First of all, thank you for your patient and detailed response,But I still have some questions about the adjustment of the high resolution period and duty cycle,Take the HRCFG register bit described in the following document as an example,

    If I configure HRCFG.CTLMODE =0, which means that MEP edge adjustment is controlled by the CMPAHR register or TBPRDHR register, then I need to configure HRCFG.EDGMODE, if I configure HRCFG.EDGMODE=01 or 10, This means that the MEP edge is controlled by the CMPAHR register, but if I configure HRCFG.EDGMODE=11, it means that the MEP edge is controlled by the TBPRDHR register,According to what you described above, the high resolution period and duty cycle can be adjusted at the same time.

    If HRCFG.CTLMODE=0 and HRCFG.EDGMODE=11 are configured respectively, I will first select a stable high resolution period TBPRDHR. So I want to use the CMPAHR register to adjust the duty cycle based on this high resolution cycle, how do I configure the  bits of the HRCFG register's EDGMODE? Is it necessary to modify the HRCFG.EDGMODE at each PWM cycle?

    Best Regards,

    Runhao

  • Hi Runhao,

    Apologies, you are correct about which parameter controls HR depending on which edge mode you are in, and I see how the wording of the TRM might also be misleading. Let me discuss the TRM description with another HRPWM expert when we are back in office tomorrow and I will revise my previous post for this thread to clarify as well.

    Best Regards,

    Allison

  • Hi Runhao,

    I am still working on clarifying this information verbiage and will update as soon as I can.

    I also wanted to ask what document the screen captures above are from? They look different than what I see currently in the F2833x TRM (https://www.ti.com/lit/pdf/sprui07). 

    Best Regards,

    Allison

  • Hi Allison,

    I'm sorry that I got the name of TRM wrong. The TRM in my screenshot above is the TRM of TMS320F2802x, which contains the relevant description of TBPRDHR, which is exactly what I was confused about, about the adjustment of high-resolution period and high-resolution duty ratio together

    I am deeply sorry for the doubts caused by my carelessness, but please kindly answer my questions in detail

    Best Regards,

    Runhao

  • Hi Runhao,

    No worries at all! I was just checking to be sure we were looking at the same document. Just to update, I've been having some discussion internally on the TRM verbiage and agree that it is confusing. I'm still working on getting a clear answer and am reaching out to design to be sure before I try to provide a detailed explanation. Apologies for the confusion and I appreciate your patience in the meantime. Feel free to send me a friend request on E2E as well to PM.

    Best Regards,

    Allison