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TMS320F28P650DK: Interrupt work after jump to app area from bootloader area.

Steven Xu
Prodigy 130 points

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: C2000WARE

Hi, Expert

   I encounter a problem when I debug the second bootloader function about TMS320F28P650DK chip.  The project can work well in bootloader area, while the interrupt function can't work after jump to app area. and other peripheral module(example: CLA, CAN, EPWM) can normal work after initialization in app area. By the way, the interrupt function can work well in bootloader area.

I guess the interrupt vector table is not configured correctly. but I can't find the reason. 

the bootloader area start address is 0x80000, and the app area start address is 0x86000.

the CMD of bootloader project is below:

// FLASH CONFIG

MEMORY
{
BEGIN : origin = 0x080000, length = 0x000002 // Update the codestart location as needed

BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B1, length = 0x00024F
RAMM1 : origin = 0x000400, length = 0x000400

RAMD0 : origin = 0x00C000, length = 0x002000
RAMD1 : origin = 0x00E000, length = 0x002000
RAMD2 : origin = 0x01A000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection
RAMD3 : origin = 0x01C000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection
RAMD4 : origin = 0x01E000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection
RAMD5 : origin = 0x020000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection

RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000

// RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
// RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory

RAMGS0 : origin = 0x010000, length = 0x002000
RAMGS1 : origin = 0x012000, length = 0x002000
RAMGS2 : origin = 0x014000, length = 0x002000
RAMGS3 : origin = 0x016000, length = 0x002000
RAMGS4 : origin = 0x018000, length = 0x002000

/* Flash Banks (128 sectors each) */
/*FLASH_BANK0 : origin = 0x080002, length = 0x1FFFE // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
*/
/*bootloader area*/
FLASH_BANK0_SEC_0_3 : origin = 0x080002, length = 0xFFE, /* on-chip Flash */
FLASH_BANK0_SEC_4_23 : origin = 0x081000, length = 0x5000, /* on-chip Flash */

/*CLA area*/
/*FLASH_BANK0_SEC_16_39 : origin = 0x084000, length = 0x6000,*/ /* on-chip Flash */
/*FLASH_BANK0_SEC_16_23 : origin = 0x085000, length = 0x1000,*/

/*bss area*/
FLASH_BANK0_SEC_24_31 : origin = 0x086000, length = 0x2000, /* on-chip Flash */

/*text area*/
FLASH_BANK0_SEC_32_55 : origin = 0x088000, length = 0x6000, /* on-chip Flash */

FLASH_BANK0_SEC_56_63 : origin = 0x08E000, length = 0x2000, /* on-chip Flash */
FLASH_BANK0_SEC_64_71 : origin = 0x090000, length = 0x2000,
FLASH_BANK0_SEC_72_79 : origin = 0x092000, length = 0x2000,
FLASH_BANK0_SEC_80_87 : origin = 0x094000, length = 0x2000,
FLASH_BANK0_SEC_88_95 : origin = 0x096000, length = 0x2000,
FLASH_BANK0_SEC_96_103 : origin = 0x098000, length = 0x2000,
FLASH_BANK0_SEC_104_111 : origin = 0x09A000, length = 0x2000,
FLASH_BANK0_SEC_112_119 : origin = 0x09C000, length = 0x2000,
FLASH_BANK0_SEC_120_127 : origin = 0x09E000, length = 0x1FF0,


FLASH_BANK1 : origin = 0x0A0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK3 : origin = 0x0E0002, length = 0x1FFFE // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK4 : origin = 0x100000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection


CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800

CLATOCPURAM : origin = 0x001480, length = 0x000080
CPUTOCLARAM : origin = 0x001500, length = 0x000080
CLATODMARAM : origin = 0x001680, length = 0x000080
DMATOCLARAM : origin = 0x001700, length = 0x000080

CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
}


SECTIONS
{
codestart : > BEGIN
.text : >> FLASH_BANK0_SEC_4_23, ALIGN(8)

.TI.ramfunc : LOAD = FLASH_BANK0_SEC_0_3,
RUN = RAMD2, // Can run in RAM for optimal cycle performance
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)

fapi : > FLASH_BANK0_SEC_0_3
{
--library=FAPI_F28P65x_EABI_v3.00.01.lib
}, ALIGN(8)

.cinit : > FLASH_BANK0_SEC_0_3, ALIGN(8)
.switch : > FLASH_BANK0_SEC_0_3, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */

.stack : > RAMM1

#if defined(__TI_EABI__)
.bss : > RAMD2
.bss:output : > RAMD2
.init_array : > FLASH_BANK0_SEC_0_3, ALIGN(8)
.const : > FLASH_BANK0_SEC_0_3, ALIGN(8)
.data : > RAMD2
.sysmem : > RAMD2
#else
.pinit : > FLASH_BANK0_SEC_0_3, ALIGN(8)
.ebss : >> RAMD2
.econst : > FLASH_BANK0_SEC_0_3, ALIGN(8)
.esysmem : > RAMD2
#endif

ramgs0 : > RAMGS0, type=NOINIT
ramgs1 : > RAMGS1, type=NOINIT
ramgs2 : > RAMGS2, type=NOINIT

MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT

DataBufferSection : > RAMD2, ALIGN(8)

and the CMD of app project is below:

MEMORY
{
BEGIN : origin = 0x080000, length = 0x000002 // Update the codestart location as needed

BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B1, length = 0x00024F
RAMM1 : origin = 0x000400, length = 0x000400

RAMD0 : origin = 0x00C000, length = 0x002000
RAMD1 : origin = 0x00E000, length = 0x002000
// RAMD2 : origin = 0x01A000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection
// RAMD3 : origin = 0x01C000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection
// RAMD4 : origin = 0x01E000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection
// RAMD5 : origin = 0x020000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection

RAMLS0LS1LS2LS3 : origin = 0x008000, length = 0x002000
/*RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800*/
RAMLS4LS5LS6LS7 : origin = 0x00A000, length = 0x002000
/* RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800*/
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000

/*RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
RAMLS9_CLA : origin = 0x006000, length = 0x002000*/ // Use only if configured as CLA program memory

RAMGS0 : origin = 0x010000, length = 0x002000
RAMGS1 : origin = 0x012000, length = 0x002000
RAMGS2 : origin = 0x014000, length = 0x002000
RAMGS3 : origin = 0x016000, length = 0x002000
RAMGS4 : origin = 0x018000, length = 0x002000

/* Flash Banks (128 sectors each) */
/*FLASH_BANK0 : origin = 0x080002, length = 0x1FFFE // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection*/

/*bootloader area*/
FLASH_BANK0_SEC_0_3 : origin = 0x080002, length = 0xFFE, /* on-chip Flash */
FLASH_BANK0_SEC_4_23 : origin = 0x081000, length = 0x5000, /* on-chip Flash */

PSU_APP_FLAG : origin = 0x086002, length = 0x0002 /*shelf app state word*/
/*CLA area*/
FLASH_BANK0_SEC_24_27 : origin = 0x086004, length = 0xFFC, /* on-chip Flash */
/*bss area*/
FLASH_BANK0_SEC_28_31 : origin = 0x087000, length = 0x1000, /* on-chip Flash */
/*text area*/
FLASH_BANK0_SEC_32_55 : origin = 0x088000, length = 0x5FFC, /* on-chip Flash */

BOOT_DONE_FLAG : origin = 0x08DFFC, length = 0x0002 /* App update success flag */

FLASH_BANK0_SEC_56_63 : origin = 0x08E000, length = 0x2000,
FLASH_BANK0_SEC_64_71 : origin = 0x090000, length = 0x2000,
FLASH_BANK0_SEC_72_79 : origin = 0x092000, length = 0x2000,
FLASH_BANK0_SEC_80_87 : origin = 0x094000, length = 0x2000,
FLASH_BANK0_SEC_88_95 : origin = 0x096000, length = 0x2000,
FLASH_BANK0_SEC_96_103 : origin = 0x098000, length = 0x2000,
FLASH_BANK0_SEC_104_111 : origin = 0x09A000, length = 0x2000,
FLASH_BANK0_SEC_112_119 : origin = 0x09C000, length = 0x2000, /* on-chip Flash */
/*FLASH_BANK0_SEC_24_31 : origin = 0x086000, length = 0x2000,*/ /* on-chip Flash */
/*FLASH_BANK0_SEC_32_39 : origin = 0x088000, length = 0x2000,*/ /* on-chip Flash */
/*FLASH_BANK0_SEC_40_47 : origin = 0x08A000, length = 0x2000,*/ /* on-chip Flash */
/*FLASH_BANK0_SEC_48_55 : origin = 0x08C000, length = 0x2000,*/ /* on-chip Flash */
/*BOOT_DONE_FLAG : origin = 0x08DFFC, length = 0x000002*/ /* App update success flag */

/*FLASH_BANK0_SEC_56_63 : origin = 0x08E000, length = 0x2000,*/ /* on-chip Flash */
/*FLASH_BANK0_SEC_64_71 : origin = 0x090000, length = 0x2000,
FLASH_BANK0_SEC_72_79 : origin = 0x092000, length = 0x2000,
FLASH_BANK0_SEC_80_87 : origin = 0x094000, length = 0x2000,
FLASH_BANK0_SEC_88_95 : origin = 0x096000, length = 0x2000,
FLASH_BANK0_SEC_96_103 : origin = 0x098000, length = 0x2000,
FLASH_BANK0_SEC_104_111 : origin = 0x09A000, length = 0x2000,
FLASH_BANK0_SEC_112_119 : origin = 0x09C000, length = 0x2000,
FLASH_BANK0_SEC_120_127 : origin = 0x09E000, length = 0x1FF0,*/

FLASH_BANK1 : origin = 0x0A0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK3 : origin = 0x0E0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK4 : origin = 0x100000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection

CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800

CLATOCPURAM : origin = 0x001480, length = 0x000080
CPUTOCLARAM : origin = 0x001500, length = 0x000080

CLATODMARAM : origin = 0x001680, length = 0x000080
DMATOCLARAM : origin = 0x001700, length = 0x000080

CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
}


SECTIONS
{
codestart : > BEGIN
.text : >> FLASH_BANK0_SEC_32_55, ALIGN(8)
.cinit : > FLASH_BANK0_SEC_28_31, ALIGN(8)
.switch : > FLASH_BANK0_SEC_28_31, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */

.stack : > RAMM1
#if defined(__TI_EABI__)
.bss : > RAMD1
.bss:output : > RAMD1
.init_array : > FLASH_BANK0_SEC_28_31, ALIGN(8)
.const : > FLASH_BANK0_SEC_28_31, ALIGN(8)
.data : > RAMD1
.sysmem : > RAMD1
#else
.pinit : > FLASH_BANK0_SEC_28_31, ALIGN(8)
.ebss : >> RAMD1
.econst : > FLASH_BANK0_SEC_28_31, ALIGN(8)
.esysmem : > RAMD1
#endif

Psu_App_Flag : > PSU_APP_FLAG
Psu_Done_Flag : > BOOT_DONE_FLAG

ramgs0 : > RAMGS0, type=NOINIT
ramgs1 : > RAMGS1, type=NOINIT
ramgs2 : > RAMGS2, type=NOINIT

MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT

#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASH_BANK0_SEC_28_31,
RUN = RAMD1,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASH_BANK0_SEC_28_31,
RUN = RAMD1,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
ALIGN(8)
#endif


/* CLA specific sections */

#if defined(__TI_EABI__)
/* CLA specific sections */
Cla1Prog : LOAD = FLASH_BANK0_SEC_24_27,
RUN = RAMLS4LS5LS6LS7,
LOAD_START(Cla1ProgLoadStart),
RUN_START(Cla1ProgRunStart),
LOAD_SIZE(Cla1ProgLoadSize),
ALIGN(4)
#else
/* CLA specific sections */
Cla1Prog : LOAD = FLASH_BANK0_SEC_24_27,
RUN = RAMLS4LS5LS6LS7,
LOAD_START(_Cla1ProgLoadStart),
RUN_START(_Cla1ProgRunStart),
LOAD_SIZE(_Cla1ProgLoadSize),
ALIGN(4)
#endif

Cla1ToCpuMsgRAM : > CLATOCPURAM
CpuToCla1MsgRAM : > CPUTOCLARAM

.scratchpad : > RAMLS0LS1LS2LS3
.bss_cla : > RAMLS0LS1LS2LS3
controlVariables : > RAMLS0LS1LS2LS3

Cla1DataRam : > RAMLS0LS1LS2LS3
cla_shared : > RAMLS0LS1LS2LS3
CLADataLS1 : > RAMLS0LS1LS2LS3


#if defined(__TI_EABI__)
.const_cla : LOAD = FLASH_BANK0_SEC_24_27,
RUN = RAMLS0LS1LS2LS3,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
ALIGN(4)
#else
.const_cla : LOAD = FLASH_BANK0_SEC_24_27,
RUN = RAMLS0LS1LS2LS3,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
ALIGN(4)
#endif
}

the instruction of Jump is below:

 

could you give me some advice?

  • 0
    TI__Genius 15080 points

    Hi Steven,

    Few questions:

    1) What is the intention of JumpToAppHandle function?

    2) I see that DINT is called before jumping to the application. Do you mean that you need interrupts enabled during the application program?

    3) Where is JumpToAppHandle() being called?

    Thanks and regards,

    Charles

  • 0 in reply to Charles Roberson
    Prodigy 130 points

    1) What is the intention of JumpToAppHandle function?

    As I want add second boot function, so my project divide into two parts, the one is application part for running the main body function, another is bootloader part for erase and update application flash area online with CAN communication. And after running over bootloader then the project need jump to application part. "JumpToAppHandle" is used to jump to application part.

     2) I see that DINT is called before jumping to the application. Do you mean that you need interrupts enabled during the application program?

    After jump to application part, the interrupt will initialize again. so it will enable during the application program.

    3) Where is JumpToAppHandle() being called?

    the JumpToAppHandle() store in bootloader area, and it will be called after checking online bootloader is done.

    by the way, if my project only running the application part without bootloader, the interrupt function works well.

  • 0 in reply to Steven Xu
    TI__Genius 15080 points

    Steven,

    You may want to consult with some of our other project examples, as this seems to be geared towards live firmware update (LFU). The F28003x device has Flash kernel examples for Flash Kernel SCI programming w/ LFU build configuration, as well as a project for CAN Flash Kernels. 

    Related project(s) pathway: C:\ti\c2000\C2000Ware_5_01_00_00\driverlib\f28003x\examples\flash

    If anything more will help as needed.

    Thanks and regards,

    Charles