TMS320F280039: CLB seems not work

Bishlant Jiang

Part Number: TMS320F280039
Other Parts Discussed in Thread: SYSCONFIG

Dear Sir,

After migrating the code to my project, I found it no output to GPIO, then I try "always 1" on out0 of CLB and I find the GPIO is still 0. here is the code:

1.enable CLB1 CLK

CpuSysRegs.PCLKCR17.bit.CLB1 = 1;
CpuSysRegs.PCLKCR17.bit.CLB2 = 0;
CpuSysRegs.PCLKCR17.bit.CLB3 = 0;
CpuSysRegs.PCLKCR17.bit.CLB4 = 0;

2.CLB init

EALLOW;

//Board_init begin.........................................................
//CLB_init.................................................................
//CLB output en
Clb1LogicCtrlRegs.CLB_OUT_EN = 0;
Clb1LogicCfgRegs.CLB_MISC_ACCESS_CTRL.bit.BLKEN = 0; //CLB_enableOutputMaskUpdates

// myCLB0 CLB_IN0/1 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
Clb1LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_0 = 0; //CLB1_GLB_MUX_OUT
Clb1LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_1 = 0; //CLB1_GLB_MUX_OUT
Clb1LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_0 = 64; //CLB_GLOBAL_IN_MUX_CLB_AUXSIG0
Clb1LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_1 = 65; //CLB_GLOBAL_IN_MUX_CLB_AUXSIG1
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_0 = 0; //Input comes from selected external input
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_1 = 0; //Input comes from selected external input
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.SYNC0 = 1; //enable sync for in0
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.SYNC1 = 1; //enable sync for in1
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.FIN0 = 0; //no filter
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.FIN1 = 0; //no filter
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.PIPE0 = 0; //CLB_disableInputPipelineMode
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.PIPE1 = 0; //CLB_disableInputPipelineMode

//CLB_setGPREG
Clb1LogicCtrlRegs.CLB_GP_REG.all = 0;
//CLB_enableCLB
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.GLOBAL_EN = 1;

//CLB_OUTPUTXBAR_init......................................................
ClbOutputXbarRegs.OUTPUTLATCHENABLE.bit.OUTPUT8 = 0; //disable latch
ClbOutputXbarRegs.OUTPUTINV.bit.OUTPUT8 = 0; //don't invert
ClbOutputXbarRegs.OUTPUT8MUX0TO15CFG.bit.MUX0 = 0; // CLB1 out0
ClbOutputXbarRegs.OUTPUT8MUXENABLE.bit.MUX0 = 1;
ClbOutputXbarRegs.OUTPUTLATCHENABLE.bit.OUTPUT7 = 0; //disable latch
ClbOutputXbarRegs.OUTPUTINV.bit.OUTPUT7 = 0; //don't invert
ClbOutputXbarRegs.OUTPUT7MUX0TO15CFG.bit.MUX2 = 0; // CLB1 out2
ClbOutputXbarRegs.OUTPUT7MUXENABLE.bit.MUX2 = 1;

//CLBXBAR_init.............................................................
// AUXSIG0 and AUXSIG1 configure
ClbXbarRegs.AUXSIG0MUX0TO15CFG.bit.MUX6 = 0; //CMPSS4_CTRIPH
ClbXbarRegs.AUXSIG1MUX0TO15CFG.bit.MUX7 = 0; //CMPSS4_CTRIPL
ClbXbarRegs.AUXSIG0MUXENABLE.bit.MUX6 = 1;
ClbXbarRegs.AUXSIG1MUXENABLE.bit.MUX7 = 1;
//Board_init end...........................................................

//
// Disable Pipeline Mode
//
// CLB_disablePipelineMode(base);
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.PIPELINE_EN = 0;
//
// Output LUT
//
//
// Equation for Output Look-Up Table Block 0 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT0, TILE1_CFG_OUTLUT_0);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN0 = 8; //Always 1 on out0

//
// Equation for Output Look-Up Table Block 1 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT1, TILE1_CFG_OUTLUT_1);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_1.bit.IN0 = 4; //FSM_0 STATE_BIT_0

//
// Equation for Output Look-Up Table Block 2 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT2, TILE1_CFG_OUTLUT_2);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN0 = 25; 

//
// Equation for Output Look-Up Table Block 3 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT3, TILE1_CFG_OUTLUT_3);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_3.bit.IN0 = 12; //FSM_1 STATE_BIT_0


//CLB_configOutputLUT(base, CLB_OUT4, TILE1_CFG_OUTLUT_4);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_4.bit.IN0 = 8;
//CLB_configOutputLUT(base, CLB_OUT5, TILE1_CFG_OUTLUT_5);

//CLB_configOutputLUT(base, CLB_OUT6, TILE1_CFG_OUTLUT_6);

//CLB_configOutputLUT(base, CLB_OUT7, TILE1_CFG_OUTLUT_7);

//
// AOC
//
//CLB_configAOC(base, CLB_AOC0, TILE1_OUTPUT_COND_CTR_0);
//CLB_configAOC(base, CLB_AOC1, TILE1_OUTPUT_COND_CTR_1);
//CLB_configAOC(base, CLB_AOC2, TILE1_OUTPUT_COND_CTR_2);
//CLB_configAOC(base, CLB_AOC3, TILE1_OUTPUT_COND_CTR_3);
//CLB_configAOC(base, CLB_AOC4, TILE1_OUTPUT_COND_CTR_4);
//CLB_configAOC(base, CLB_AOC5, TILE1_OUTPUT_COND_CTR_5);
//CLB_configAOC(base, CLB_AOC6, TILE1_OUTPUT_COND_CTR_6);
//CLB_configAOC(base, CLB_AOC7, TILE1_OUTPUT_COND_CTR_7);

//
// LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
// CLB_selectLUT4Inputs and CLB_configLUT4Function
//

//
// LUT Configuration
//
//CLB_selectLUT4Inputs(base, TILE1_CFG_LUT4_IN0, TILE1_CFG_LUT4_IN1, TILE1_CFG_LUT4_IN2, TILE1_CFG_LUT4_IN3);
//CLB_configLUT4Function(base, TILE1_CFG_LUT4_FN10, TILE1_CFG_LUT4_FN2);

//
// FSM 0 - 2 are configured in <file>
//
// State 0 output equation for Finite State Machine 0 for TILE1: ((~s0)&e0)|(s0&e1)
// User Description for Finite State Machine 0 for TILE1
/*
complementary ePWMA
*/
// State 0 output equation for Finite State Machine 1 for TILE1: ((~s0)&e0)|(s0&(~e1))
// User Description for Finite State Machine 1 for TILE1
/*
complementary ePWMB
*/

//
// FSM
//
//CLB_selectFSMInputs(base, TILE1_CFG_FSM_EXT_IN0, TILE1_CFG_FSM_EXT_IN1, TILE1_CFG_FSM_EXTRA_IN0, TILE1_CFG_FSM_EXTRA_IN1);
//CLB_configFSMNextState(base, TILE1_CFG_FSM_NEXT_STATE_0, TILE1_CFG_FSM_NEXT_STATE_1, TILE1_CFG_FSM_NEXT_STATE_2);
//CLB_configFSMLUTFunction(base, TILE1_CFG_FSM_LUT_FN10, TILE1_CFG_FSM_LUT_FN2);

Clb1LogicCfgRegs.CLB_FSM_EXTERNAL_IN0.all = TILE1_CFG_FSM_EXT_IN0;
Clb1LogicCfgRegs.CLB_FSM_EXTERNAL_IN1.all = TILE1_CFG_FSM_EXT_IN1;
Clb1LogicCfgRegs.CLB_FSM_EXTRA_IN0.all = TILE1_CFG_FSM_EXTRA_IN0;
Clb1LogicCfgRegs.CLB_FSM_EXTRA_IN1.all = TILE1_CFG_FSM_EXTRA_IN1;
Clb1LogicCfgRegs.CLB_FSM_NEXT_STATE_0.all = TILE1_CFG_FSM_NEXT_STATE_0;
Clb1LogicCfgRegs.CLB_FSM_NEXT_STATE_1.all = TILE1_CFG_FSM_NEXT_STATE_1;
Clb1LogicCfgRegs.CLB_FSM_NEXT_STATE_2.all = TILE1_CFG_FSM_NEXT_STATE_2;
Clb1LogicCfgRegs.CLB_FSM_LUT_FN1_0.all = TILE1_CFG_FSM_LUT_FN10;
Clb1LogicCfgRegs.CLB_FSM_LUT_FN2.all = TILE1_CFG_FSM_LUT_FN2;
//
// Counter 0 - 2 are configured in <file>
//
// User Description for Counter 0 for TILE1
/*
reset counter with input 0(CMPSS4 TRIPH) and load with input 1(CMPSS4 TRIP-
L)
*/
// User Description for Counter 1 for TILE1
/*
PWMA
*/
// User Description for Counter 2 for TILE1
/*
PWMB
*/

//
// Counters
//
//CLB_selectCounterInputs(base, TILE1_CFG_COUNTER_RESET, TILE1_CFG_COUNTER_EVENT, TILE1_CFG_COUNTER_MODE_0, TILE1_CFG_COUNTER_MODE_1);
//CLB_configMiscCtrlModes(base, TILE1_CFG_MISC_CONTROL);
//CLB_configCounterLoadMatch(base, CLB_CTR0, TILE1_COUNTER_0_LOAD_VAL, TILE1_COUNTER_0_MATCH1_VAL, TILE1_COUNTER_0_MATCH2_VAL);
//CLB_configCounterLoadMatch(base, CLB_CTR1, TILE1_COUNTER_1_LOAD_VAL, TILE1_COUNTER_1_MATCH1_VAL, TILE1_COUNTER_1_MATCH2_VAL);
//CLB_configCounterLoadMatch(base, CLB_CTR2, TILE1_COUNTER_2_LOAD_VAL, TILE1_COUNTER_2_MATCH1_VAL, TILE1_COUNTER_2_MATCH2_VAL);
//CLB_configCounterTapSelects(base, TILE1_CFG_TAP_SEL);

Clb1LogicCfgRegs.CLB_COUNT_RESET.all = TILE1_CFG_COUNTER_RESET;
Clb1LogicCfgRegs.CLB_COUNT_EVENT.all = TILE1_CFG_COUNTER_EVENT;
Clb1LogicCfgRegs.CLB_COUNT_MODE_0.all = TILE1_CFG_COUNTER_MODE_0;
Clb1LogicCfgRegs.CLB_COUNT_MODE_1.all = TILE1_CFG_COUNTER_MODE_1;
Clb1LogicCfgRegs.CLB_MISC_CONTROL.all = TILE1_CFG_MISC_CONTROL;

Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_0_LOAD;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_0_LOAD_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_0_MATCH1;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_0_MATCH1_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_0_MATCH2;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_0_MATCH2_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;

Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_1_LOAD;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_1_LOAD_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_1_MATCH1;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_1_MATCH1_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_1_MATCH2;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_1_MATCH2_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;

Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_2_LOAD;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_2_LOAD_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_2_MATCH1;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_2_MATCH1_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_2_MATCH2;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_2_MATCH2_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;

//
// HLC is configured in <file>
//

//
// HLC
//
//CLB_configHLCEventSelect(base, TILE1_HLC_EVENT_SEL);
//CLB_setHLCRegisters(base, TILE1_HLC_R0_INIT, TILE1_HLC_R1_INIT, TILE1_HLC_R2_INIT, TILE1_HLC_R3_INIT);

//for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
//{
// CLB_programHLCInstruction(base, i, TILE1HLCInstr[i]);
//}

EDIS;

3.GPIO MUX

GPIO0 mux to 11(CLB_OUTPUTXBAR8)

EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 2;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 3; // Configure GPIO0 as CLB output
EDIS;

any ideas please, thanks.

over 1 year ago

0 Omer Amir over 1 year ago

TI__Mastermind 30185 points

Hello Bishlant,

(If you aren't opposed to it, I will insert your code into a code block so that it doesn't clutter this post)

Bishlant Jiang said:
After migrating the code to my project, I found it no output to GPIO, then I try "always 1" on out0 of CLB and I find the GPIO is still 0.

Are you using SysConfig to configure the CLB/GPIO? If so, can you provide both .syscfg or sets of source files (before and after migration)? Based on your phrasing, it sounds like the GPIO toggle worked fine on the device which previously held this code, is that correct?

Bishlant Jiang said:
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 2;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 3; // Configure GPIO0 as CLB output
EDIS;

Besides the above code, I don't see any code for your GPIO configuration, is there something you haven't provided here?

0 Bishlant Jiang over 1 year ago in reply to Omer Amir

Prodigy 90 points

Hello Omer,

Please go ahead.---If you aren't opposed to it, I will insert your code into a code block so that it doesn't clutter this post

Maybe due to the IT policy, i can't upload the files here. can i mail to you?

Omer Amir said:
it sounds like the GPIO toggle worked fine on the device which previously held this code, is that correct?

the GPIO was funciton as ePWM before and works fine.

isn't this the configuration for GPIO? anything i missed?

EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 2;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 3; // Configure GPIO0 as CLB output
EDIS;

0 Bishlant Jiang over 1 year ago in reply to Omer Amir

Prodigy 90 points

/*
 *  ======== clb.c ========
 *  DO NOT EDIT - This file is generated by the SysConfig tool.
 */

#include "driverlib.h"
#include "device.h"
#include "clb_config.h"
#include "clb.h"


const uint32_t TILE1_HLC_initFIFOData[4] = {TILE1_HLC_FIFO0_INIT, TILE1_HLC_FIFO1_INIT, TILE1_HLC_FIFO2_INIT, TILE1_HLC_FIFO3_INIT};

uint16_t TILE1HLCInstr[CLB_NUM_HLC_INSTR + 1] =
{
    TILE1_HLCINSTR_0,
    TILE1_HLCINSTR_1,
    TILE1_HLCINSTR_2,
    TILE1_HLCINSTR_3,
    TILE1_HLCINSTR_4,
    TILE1_HLCINSTR_5,
    TILE1_HLCINSTR_6,
    TILE1_HLCINSTR_7,
    TILE1_HLCINSTR_8,
    TILE1_HLCINSTR_9,
    TILE1_HLCINSTR_10,
    TILE1_HLCINSTR_11,
    TILE1_HLCINSTR_12,
    TILE1_HLCINSTR_13,
    TILE1_HLCINSTR_14,
    TILE1_HLCINSTR_15,
    TILE1_HLCINSTR_16,
    TILE1_HLCINSTR_17,
    TILE1_HLCINSTR_18,
    TILE1_HLCINSTR_19,
    TILE1_HLCINSTR_20,
    TILE1_HLCINSTR_21,
    TILE1_HLCINSTR_22,
    TILE1_HLCINSTR_23,
    TILE1_HLCINSTR_24,
    TILE1_HLCINSTR_25,
    TILE1_HLCINSTR_26,
    TILE1_HLCINSTR_27,
    TILE1_HLCINSTR_28,
    TILE1_HLCINSTR_29,
    TILE1_HLCINSTR_30,
    TILE1_HLCINSTR_31
};



void initTILE1(uint32_t base)
{
    uint16_t i;
    //
    //  Pipeline Mode
    //
    CLB_disablePipelineMode(base);
    //
    //  Output LUT
    //
    //
    //  Equation for Output Look-Up Table Block 0 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT0, TILE1_CFG_OUTLUT_0);

    //
    //  Equation for Output Look-Up Table Block 1 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT1, TILE1_CFG_OUTLUT_1);

    //
    //  Equation for Output Look-Up Table Block 2 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT2, TILE1_CFG_OUTLUT_2);

    //
    //  Equation for Output Look-Up Table Block 3 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT3, TILE1_CFG_OUTLUT_3);

    //
    //  Equation for Output Look-Up Table Block 4 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT4, TILE1_CFG_OUTLUT_4);

    CLB_configOutputLUT(base, CLB_OUT5, TILE1_CFG_OUTLUT_5);
    
    CLB_configOutputLUT(base, CLB_OUT6, TILE1_CFG_OUTLUT_6);

    CLB_configOutputLUT(base, CLB_OUT7, TILE1_CFG_OUTLUT_7);

    //
    //  AOC
    //
    CLB_configAOC(base, CLB_AOC0, TILE1_OUTPUT_COND_CTR_0);
    CLB_configAOC(base, CLB_AOC1, TILE1_OUTPUT_COND_CTR_1);
    CLB_configAOC(base, CLB_AOC2, TILE1_OUTPUT_COND_CTR_2);
    CLB_configAOC(base, CLB_AOC3, TILE1_OUTPUT_COND_CTR_3);
    CLB_configAOC(base, CLB_AOC4, TILE1_OUTPUT_COND_CTR_4);
    CLB_configAOC(base, CLB_AOC5, TILE1_OUTPUT_COND_CTR_5);
    CLB_configAOC(base, CLB_AOC6, TILE1_OUTPUT_COND_CTR_6);
    CLB_configAOC(base, CLB_AOC7, TILE1_OUTPUT_COND_CTR_7);

    //
    // LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
    // CLB_selectLUT4Inputs and CLB_configLUT4Function
    //

    //
    //  LUT Configuration
    //
    CLB_selectLUT4Inputs(base, TILE1_CFG_LUT4_IN0, TILE1_CFG_LUT4_IN1, TILE1_CFG_LUT4_IN2, TILE1_CFG_LUT4_IN3);
    CLB_configLUT4Function(base, TILE1_CFG_LUT4_FN10, TILE1_CFG_LUT4_FN2);

    //
    // FSM 0 - 2 are configured in <file>
    //
    //  State 0 output equation for Finite State Machine 0 for TILE1: ((~s0)&e0)|(s0&e1)
    //  User Description for Finite State Machine 0 for TILE1
    /*
        complementary ePWMA
    */
    //  State 0 output equation for Finite State Machine 1 for TILE1: ((~s0)&e0)|(s0&(~e1))
    //  User Description for Finite State Machine 1 for TILE1
    /*
        complementary ePWMB
    */

    //
    //  FSM
    //
    CLB_selectFSMInputs(base, TILE1_CFG_FSM_EXT_IN0, TILE1_CFG_FSM_EXT_IN1, TILE1_CFG_FSM_EXTRA_IN0, TILE1_CFG_FSM_EXTRA_IN1);
    CLB_configFSMNextState(base, TILE1_CFG_FSM_NEXT_STATE_0, TILE1_CFG_FSM_NEXT_STATE_1, TILE1_CFG_FSM_NEXT_STATE_2);
    CLB_configFSMLUTFunction(base, TILE1_CFG_FSM_LUT_FN10, TILE1_CFG_FSM_LUT_FN2);

    //
    // Counter 0 - 2 are configured in <file>
    //
    //  User Description for Counter 0 for TILE1
    /*
        reset counter with input 0(CMPSS4 TRIPH) and load with input 1(CMPSS4 TRIP-
		L)
    */
    //  User Description for Counter 1 for TILE1
    /*
        PWMA
    */
    //  User Description for Counter 2 for TILE1
    /*
        PWMB
    */

    //
    //  Counters
    //
    CLB_selectCounterInputs(base, TILE1_CFG_COUNTER_RESET, TILE1_CFG_COUNTER_EVENT, TILE1_CFG_COUNTER_MODE_0, TILE1_CFG_COUNTER_MODE_1);
    CLB_configMiscCtrlModes(base, TILE1_CFG_MISC_CONTROL);
    CLB_configCounterLoadMatch(base, CLB_CTR0, TILE1_COUNTER_0_LOAD_VAL, TILE1_COUNTER_0_MATCH1_VAL, TILE1_COUNTER_0_MATCH2_VAL);
    CLB_configCounterLoadMatch(base, CLB_CTR1, TILE1_COUNTER_1_LOAD_VAL, TILE1_COUNTER_1_MATCH1_VAL, TILE1_COUNTER_1_MATCH2_VAL);
    CLB_configCounterLoadMatch(base, CLB_CTR2, TILE1_COUNTER_2_LOAD_VAL, TILE1_COUNTER_2_MATCH1_VAL, TILE1_COUNTER_2_MATCH2_VAL);
    CLB_configCounterTapSelects(base, TILE1_CFG_TAP_SEL);

    //
    // HLC is configured in <file>
    //

    //
    // HLC
    //
    CLB_configHLCEventSelect(base, TILE1_HLC_EVENT_SEL);
    CLB_setHLCRegisters(base, TILE1_HLC_R0_INIT, TILE1_HLC_R1_INIT, TILE1_HLC_R2_INIT, TILE1_HLC_R3_INIT);

    for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
    {
        CLB_programHLCInstruction(base, i, TILE1HLCInstr[i]);
    }
}

0 Bishlant Jiang over 1 year ago in reply to Omer Amir

Prodigy 90 points

/*
 *  ======== clb.h ========
 *  DO NOT EDIT - This file is generated by the SysConfig tool.
 */
#ifndef ti_clb_h
#define ti_clb_h

#include <stdint.h>

#ifdef __cplusplus
extern "C" {                // support C++ sources
#endif

// HLC Instruction Register Field definitions
#define HLC_OPCODE_R0 0x0
#define HLC_OPCODE_R1 0x1
#define HLC_OPCODE_R2 0x2
#define HLC_OPCODE_R3 0x3
#define HLC_OPCODE_C0 0x4
#define HLC_OPCODE_C1 0x5
#define HLC_OPCODE_C2 0x6

#define HLC_OPCODE_MOV    0x00
#define HLC_OPCODE_MOV_T1 0x01
#define HLC_OPCODE_MOV_T2 0x02
#define HLC_OPCODE_PUSH   0x03
#define HLC_OPCODE_PULL   0x04
#define HLC_OPCODE_ADD    0x05
#define HLC_OPCODE_SUB    0x06
#define HLC_OPCODE_INTR   0x07

//---------------------------------------------------------------------------
// TILE1
//---------------------------------------------------------------------------
#define TILE1_PIPELINE_MODE 0
#define TILE1_CFG_OUTLUT_0 0x550008
#define TILE1_CFG_OUTLUT_1 0x550004
#define TILE1_CFG_OUTLUT_2 0x550019
#define TILE1_CFG_OUTLUT_3 0x55000c
#define TILE1_CFG_OUTLUT_4 0x550018
#define TILE1_CFG_OUTLUT_5 0x0
#define TILE1_CFG_OUTLUT_6 0x0
#define TILE1_CFG_OUTLUT_7 0x0

#define TILE1_CFG_LUT4_IN0   0x0
#define TILE1_CFG_LUT4_IN1   0x0
#define TILE1_CFG_LUT4_IN2   0x0
#define TILE1_CFG_LUT4_IN3   0x0
#define TILE1_CFG_LUT4_FN10  ((0x00000) | 0x0)
#define TILE1_CFG_LUT4_FN2   0x0

#define TILE1_CFG_FSM_EXT_IN0      0x26b
#define TILE1_CFG_FSM_EXT_IN1      0x42
#define TILE1_CFG_FSM_EXTRA_IN0    0x0
#define TILE1_CFG_FSM_EXTRA_IN1    0x0
#define TILE1_CFG_FSM_NEXT_STATE_0 ((0x00000) | 0xfa50)
#define TILE1_CFG_FSM_NEXT_STATE_1 ((0x00000) | 0x50fa)
#define TILE1_CFG_FSM_NEXT_STATE_2 ((0x00000) | 0x0)
#define TILE1_CFG_FSM_LUT_FN10     ((0x00000) | 0x0)
#define TILE1_CFG_FSM_LUT_FN2      0x0
#define TILE1_FSM_MISC_CONTROL     0x0

#define TILE1_CFG_COUNTER_RESET   0xc38
#define TILE1_CFG_COUNTER_EVENT   0x19
#define TILE1_CFG_COUNTER_MODE_0  0x460
#define TILE1_CFG_COUNTER_MODE_1  0x2100
#define TILE1_CFG_TAP_SEL          0x0
#define TILE1_CFG_MISC_CONTROL    (0x0 | TILE1_FSM_MISC_CONTROL)

#define TILE1_COUNTER_0_MATCH1_VAL  0
#define TILE1_COUNTER_0_MATCH2_VAL  1
#define TILE1_COUNTER_0_LOAD_VAL    1
#define TILE1_COUNTER_1_MATCH1_VAL  3
#define TILE1_COUNTER_1_MATCH2_VAL  0
#define TILE1_COUNTER_1_LOAD_VAL    0
#define TILE1_COUNTER_2_MATCH1_VAL  3
#define TILE1_COUNTER_2_MATCH2_VAL  0
#define TILE1_COUNTER_2_LOAD_VAL    0


#define TILE1_SPI_EN 0

#define TILE1_HLC_EVENT_SEL 0x0
#define TILE1_HLC_R0_INIT 0
#define TILE1_HLC_R1_INIT 0
#define TILE1_HLC_R2_INIT 0
#define TILE1_HLC_R3_INIT 0

#define TILE1_HLC_FIFO0_INIT 0
#define TILE1_HLC_FIFO1_INIT 0
#define TILE1_HLC_FIFO2_INIT 0
#define TILE1_HLC_FIFO3_INIT 0

#define TILE1_HLCINSTR_0	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_1	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_2	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_3	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_4	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_5	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_6	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_7	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_8	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_9	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_10	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_11	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_12	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_13	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_14	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_15	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_16	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_17	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_18	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_19	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_20	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_21	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_22	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_23	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_24	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_25	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_26	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_27	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_28	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_29	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_30	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_31	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)




#define TILE1_OUTPUT_COND_CTR_0 0x0
#define TILE1_OUTPUT_COND_CTR_1 0x0
#define TILE1_OUTPUT_COND_CTR_2 0x0
#define TILE1_OUTPUT_COND_CTR_3 0x0
#define TILE1_OUTPUT_COND_CTR_4 0x0
#define TILE1_OUTPUT_COND_CTR_5 0x0
#define TILE1_OUTPUT_COND_CTR_6 0x0
#define TILE1_OUTPUT_COND_CTR_7 0x0

void initTILE1(uint32_t base);

#ifdef __cplusplus
}
#endif

#endif // ti_clb_h

here are the clb_config.h and .c

0 Omer Amir over 1 year ago in reply to Bishlant Jiang

TI__Mastermind 30185 points

Hello Bishlant,

Bishlant Jiang said:
Maybe due to the IT policy, i can't upload the files here. can i mail to you?

If you add me as a friend on E2E, you can privately message me your code if you have any restrictions on posting code publicly.

Bishlant Jiang said:
the GPIO was funciton as ePWM before and works fine.

isn't this the configuration for GPIO? anything i missed?

If you're trying to use the GPIO as an output for the CLB, then you should configure it as an output. If you used it as an ePWM output previously and used SysConfig, the tool would have configured the pin for the ePWM peripheral and it would have worked fine. CLB is not the same in this aspect, since you will be relying on the crossbars to route the signal from the CLB to the GPIO. As such, the GPIO will need to be configured as an output.

Also, you set the GPIO mux to 2, when it should be a multiple of 4 (or set to 0) if you are using it as a GPIO pin:

0 Bishlant Jiang over 1 year ago in reply to Omer Amir

Prodigy 90 points

Shouldn't it be 11(CLB_OUTPUTXBAR8) here for GPIO mux?

the CLB output xbar config as follow, when i try to config GPIO0 as output, it shows that "resource conflict"(GPIO0/79 is currently in use by myCLB_OUTPUTXBAR0)

0 Bishlant Jiang over 1 year ago in reply to Omer Amir

Prodigy 90 points

Omer Amir said:
As such, the GPIO will need to be configured as an output.

If I understand right, you mean that the GPIO direction should be config as output.

EALLOW;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO1 = 1;
EDIS;

but I think the GPIO mux should be 11, not 0 or 4(8/12)

Omer Amir said:
Also, you set the GPIO mux to 2, when it should be a multiple of 4 (or set to 0) if you are using it as a GPIO pin:

I tried the above configuration, still no output from GPIO0.

then I tried with CLB_OUT_EN set to 0x0F, stilll the same, GPIO 0 is 0, not 1.

Clb1LogicCtrlRegs.CLB_OUT_EN = 0x0F;
Clb1LogicCfgRegs.CLB_MISC_ACCESS_CTRL.bit.BLKEN = 0; //CLB_enableOutputMaskUpdates

0 Bishlant Jiang over 1 year ago in reply to Bishlant Jiang

Prodigy 90 points

0 Bishlant Jiang over 1 year ago in reply to Bishlant Jiang

Prodigy 90 points

it shows here that GPIO MUX can passthrough the signal from CLB OUTPUSXBAR

0 Omer Amir over 1 year ago in reply to Bishlant Jiang

TI__Mastermind 30185 points

Hello Bishlant,

Bishlant Jiang said:
the CLB output xbar config as follow, when i try to config GPIO0 as output, it shows that "resource conflict"(GPIO0/79 is currently in use by myCLB_OUTPUTXBAR0)

I see, there was a misunderstanding on my part with regards to how the XBAR configures the output. From your initial post you have the GPIO mux (which is not the same as the XBAR configuration) set as 2, but to use the GPIO pin as a GPIO it needs to be configured as 0, 4, 8, or 12. There are a few other things to test to help debug this.

Try to use GPIO0 by itself and toggle it as an output to make sure the pin itself is not having a problem. Try using a different GPIO as the CLB output.
Please verify your CLB operates as expected use the simulation tool. There are instructions in section 3.4 Creating the CLB Diagram of the CLB Tool User's Guide. Make sure you have followed the installation instructions in section 2.3 first so that you have the proper tool to view the simulation output.
Create a diff of the code generated from the device you're migrating from to the device you're migrating to, find out why the code changes are present. This means not just copying and pasting the code here, but looking at the code on your end and finding what lines are different. The CLB has different types, so depending on what device you're migrating from there should be expected changes. What device are you migrating from?

0 Bishlant Jiang over 1 year ago in reply to Omer Amir

Prodigy 90 points

Hi Omer,

for the point 1, I confirm that the GPIO0 works fine when it's an GPIO output.

the result using simulation tool is ok. sorry I may make you misunderstanding, it's a new design with CLB, I design the CLB using system config tool and simulate the design, all works well then I "migrate" the code generated(clb_config.c, board.c) to my project(it's a bit field project, so I modified all the lib function like CLB_configOutputLUT(base, CLB_OUT0, TILE1_CFG_OUTLUT_0); to Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN0 = 8;

0 Omer Amir over 1 year ago in reply to Bishlant Jiang

TI__Mastermind 30185 points

I understand now, we can continue discussing through private message to help resolve the issue. I will post the resolution here once we have determined the reason for it.

+1 Omer Amir over 1 year ago in reply to Omer Amir

TI__Mastermind 30185 points

Hello Bishlant,

As tested on our side, the GPIO does get set when the CLB output XBAR is used to output a signal from the CLB, please make sure that the CLB module has a Tile Design attached and initialized before running your code. There is no hardware limitation in configuring the GPIO to output a signal from the CLB.

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F280039: CLB seems not work