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TMS320F28P659DK-Q1: SPI time sequence

Wenting Wu
Intellectual 2495 points

Part Number: TMS320F28P659DK-Q1
Other Parts Discussed in Thread: TCAN1146-Q1

Hello Expert,

May I ask should F28P659 follow the time sequence seriously? In F28P659 datasheet, the delay between SPI's CS and CLK is from -3ns to 3ns. Can this time be set up larger than 100ns?

F28P659-Q1's SPI is used to communicate with TCAN1146-Q1's SPI. 

While, TCAN1146-Q1 has a time sequence requirement that its chip selection time should be larger than 100ns. (Tcsh>100ns)

Do we have any method to let F28P659-Q1's SPI signal to meet the request from TCAN1146-Q1's SPI?

Best regards,

wenting 

  • 0
    TI__Expert 6000 points

    Hi,

    Our SPI expert is OOO today , Please expect response in next couple of days.

    Regards,

    Rajeshwary

  • 0 in reply to Rajeshwary Nitin Bongirwar
    TI__Intellectual 2495 points

    Hello Raje,

    Is SPI expert back today?

  • +1
    TI__Mastermind 20175 points

    Hi Wenting,

    Can you clarify if your question is regarding the setup time, hold time, delay time, and/or valid time? These are related but different characteristics of the SPI where setup time is the time before the rising edge of the clock and hold time is the valid time after. 

    Wenting Wu said:
    In F28P659 datasheet, the delay between SPI's CS and CLK is from -3ns to 3ns. Can this time be set up larger than 100ns?

    Assuming you are in Clock Phase 1 where the F28P65x is the controller device, according to table 6.15.7.1.2 in the F28P65x DS, the tv(PTE)M (valid time, SPICLK to SPIPTE invalid) of -3 to 3 ns which was highlighted in the attached image, is a characteristic of the protocol which means it cannot be modified by the user explicitly. 

    Wenting Wu said:
    While, TCAN1146-Q1 has a time sequence requirement that its chip selection time should be larger than 100ns. (Tcsh>100ns)

    According to table 8.9 in the TCAN1146-Q1 DS, the tCSH (hold time) and tCSS (setup time) of 100 ns is a characteristic of the protocol which means it cannot be modified by the user explicitly. Since the characteristics are ultimately different, my suggestion would be to manually control the CS using a GPIO with added delays in software to meet timing requirements.

    Aishwarya