TMS320F28379D: DMA SPI: Not receiving correct data...Only 1 byte is non-zero

stevenh

Guru 20045 points

Part Number: TMS320F28379D
Other Parts Discussed in Thread: SYSCONFIG, C2000WARE

Hello,

I am trying to retrieve ethernet data from a W5500 using the TMS320F28379D's SPI and DMA. Please see contents of my project's sysconfig file below.

I can see the MISO data on the oscilloscope, however, I am not seeing the correct data in the Rx Buffer after the SPI Rx DMA's transfer complete interrupt occurs.

Also, the SPI Rx FIFO buffer still has data in it.

What is wrong with my SPI/DMA configuration.

Stephen

/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "F2837xD" --package "F2837xD_337ZWT" --part "F2837xD_337ZWT" --context "CPU1" --product "C2000WARE@5.01.00.00"
* @versions {"tool":"1.18.0+3266"}
*/

/**
* Import the modules used in this configuration.
*/
const device_support = scripting.addModule("/driverlib/device_support.js");
const flash = scripting.addModule("/driverlib/flash.js", {}, false);
const flash1 = flash.addInstance();
const sci = scripting.addModule("/driverlib/sci.js", {}, false);
const sci1 = sci.addInstance();
const spi = scripting.addModule("/driverlib/spi.js", {}, false);
const spi1 = spi.addInstance();
const sysctl = scripting.addModule("/driverlib/sysctl.js");
const FREERTOS = scripting.addModule("/kernel/freertos_tool/FREERTOS", {}, false);
const FREERTOS1 = FREERTOS.addInstance();

/**
* Write custom configuration values to the imported modules.
*/
const divider4 = system.clockTree["LOSPCP"];
divider4.divideValue = 6;

const divider5 = system.clockTree["SYSCLKDIVSEL"];
divider5.divideValue = 1;

const multiplier4 = system.clockTree["PLL_IMULT"];
multiplier4.multiplyValue = 10;

const mux8 = system.clockTree["XTAL_OR_X1"];
mux8.inputSelect = "X1";

flash1.$name = "myFMC0";
flash1.enableECC = false;

sci1.useInterrupts = false;
sci1.$name = "mySCIB";
sci1.baudRates = 38400;
sci1.sci.$assign = "SCIB";

spi1.transferProtocol = "SPI_PROT_POL0PHA1";
spi1.$name = "SPIA_HW";
spi1.mode = "SPI_MODE_CONTROLLER";
spi1.bitRate = 6666666;
spi1.dataWidth = "8";
spi1.emulationMode = "SPI_EMULATION_STOP_AFTER_TRANSMIT";
spi1.useDMARX = true;
spi1.useDMATX = true;
spi1.registerInterrupts = true;
spi1.txFifo = "SPI_FIFO_TX8";
spi1.rxFifo = "SPI_FIFO_RX4";
spi1.enabledFIFOInterrupts = ["SPI_INT_RXFF"];
spi1.useInterrupts = false;
spi1.spi.$assign = "SPIA";
spi1.spiRXDMA.databusWidthConfig = scripting.forceWrite("DMA_CFG_SIZE_16BIT");
spi1.spiRXDMA.transferSize = 16;
spi1.spiRXDMA.burstSize = 8;
spi1.spiRXDMA.destAddressInputMode = "VARIABLE";
spi1.spiRXDMA.destAddressVariable = "RxSpiDMAData";
spi1.spiRXDMA.useInterrupts = true;
spi1.spiRXDMA.registerInterrupts = true;
spi1.spiRXDMA.enableInterrupts = true;
spi1.spiRXDMA.enableTriggers = true;
spi1.spiRXDMA.interruptMode = "DMA_INT_AT_END";
spi1.spiRXDMA.emulationMode = "DMA_EMULATION_FREE_RUN";
spi1.spiRXDMA.dmaInt.enableInterrupt = true;
spi1.spiTXDMA.databusWidthConfig = scripting.forceWrite("DMA_CFG_SIZE_16BIT");
spi1.spiTXDMA.dmaBase = "DMA_CH2_BASE";
spi1.spiTXDMA.srcAddressInputMode = "VARIABLE";
spi1.spiTXDMA.srcAddressVariable = "TxSpiDMAData";
spi1.spiTXDMA.burstSize = 8;
spi1.spiTXDMA.transferSize = 16;
spi1.spiTXDMA.useInterrupts = true;
spi1.spiTXDMA.registerInterrupts = true;
spi1.spiTXDMA.enableInterrupts = true;
spi1.spiTXDMA.enableTriggers = true;
spi1.spiTXDMA.interruptMode = "DMA_INT_AT_END";
spi1.spiTXDMA.dmaInt.enableInterrupt = true;

sysctl.enable_SYSCTL_PERIPH_CLK_CLA1 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_HRPWM = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EMIF1 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EMIF2 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM1 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM2 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM3 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM4 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM5 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM6 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM7 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM8 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM9 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM10 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM11 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EPWM12 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ECAP1 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ECAP2 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ECAP3 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ECAP4 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ECAP5 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ECAP6 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EQEP1 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EQEP2 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_EQEP3 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_SD1 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_SD2 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_SCIA = false;
sysctl.enable_SYSCTL_PERIPH_CLK_SCIC = false;
sysctl.enable_SYSCTL_PERIPH_CLK_SCIB = false;
sysctl.enable_SYSCTL_PERIPH_CLK_SCID = false;
sysctl.enable_SYSCTL_PERIPH_CLK_SPIB = false;
sysctl.enable_SYSCTL_PERIPH_CLK_SPIC = false;
sysctl.enable_SYSCTL_PERIPH_CLK_I2CA = false;
sysctl.enable_SYSCTL_PERIPH_CLK_I2CB = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CANA = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CANB = false;
sysctl.enable_SYSCTL_PERIPH_CLK_MCBSPA = false;
sysctl.enable_SYSCTL_PERIPH_CLK_MCBSPB = false;
sysctl.enable_SYSCTL_PERIPH_CLK_UPPA = false;
sysctl.enable_SYSCTL_PERIPH_CLK_USBA = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ADCA = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ADCB = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ADCD = false;
sysctl.enable_SYSCTL_PERIPH_CLK_ADCC = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CMPSS1 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CMPSS3 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CMPSS4 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CMPSS2 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CMPSS5 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CMPSS6 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CMPSS7 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_CMPSS8 = false;
sysctl.enable_SYSCTL_PERIPH_CLK_DACA = false;
sysctl.enable_SYSCTL_PERIPH_CLK_DACB = false;
sysctl.enable_SYSCTL_PERIPH_CLK_DACC = false;
sysctl.secControllerFrame2 = "SYSCTL_SEC_CONTROLLER_DMA";
sysctl.secControllerFrame1 = "SYSCTL_SEC_CONTROLLER_DMA";

FREERTOS1.$name = "myFREERTOS0";
FREERTOS1.MINIMAL_STACK_SIZE = 256;
FREERTOS1.CPU_CLOCK_HZ = 200000000;
FREERTOS1.tasks.create(1);
FREERTOS1.tasks[0].taskPointer = "Task_4ms";
FREERTOS1.tasks[0].$name = "TASK_4milliseconds";
FREERTOS1.tasks[0].taskStackSize = 1300;
FREERTOS1.tasks[0].taskPriority = 18;
FREERTOS1.semaphores.create(2);
FREERTOS1.semaphores[0].$name = "Task100ms_binarySem1";
FREERTOS1.semaphores[1].$name = "Task10ms_binarySem1";

/**
* Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
* version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
* re-solve from scratch.
*/
sci1.sci.scirxdPin.$suggestSolution = "GPIO11";
sci1.sci.scitxdPin.$suggestSolution = "GPIO10";
spi1.spi.spi_picoPin.$suggestSolution = "GPIO16";
spi1.spi.spi_pociPin.$suggestSolution = "GPIO17";
spi1.spi.spi_clkPin.$suggestSolution = "GPIO18";
spi1.spi.spi_ptePin.$suggestSolution = "GPIO19";

over 1 year ago

0 Allison Nguyen over 1 year ago

TI__Mastermind 23470 points

Hi stevenh,

stevenh said:
I can see the MISO data on the oscilloscope, however, I am not seeing the correct data in the Rx Buffer after the SPI Rx DMA's transfer complete interrupt occurs.

Also, the SPI Rx FIFO buffer still has data in it.

When you say that you are not seeing correct data in the RX buffer, do you mean the SPI receive buffer? Or do you mean the buffer in memory? Is the SPI RX FIFO receiving correct data? If my understanding is correct, it sounds like something is going wrong with the DMA configurations.

Did you already reference the TRM sections for SPI DMA (18.3.8 SPI DMA Transfers)? There are calculations to be sure to follow to set the DMA burst size and transfer size properly to match your FIFO TX/RX interrupt levels. The burst size should be as seen in the calculation examples.

For example:
- For TX with DMA, since TXFFIL is 8, you would need a burst size of 7.
- For RX with DMA, since RXFFIL is 4, you would need a burst size of 3.

Best Regards,

Allison

0 stevenh over 1 year ago in reply to Allison Nguyen

Guru 20045 points

Thanks for the quick reply.

I think I see one issue: the bust step for source and destination are set to 0.

On a previous project I had completed using McBSP and DMA I had set all of them to 1 (i.e. add 1 to the address)

I will test with all them set to 1 and then get back with you.

JFYI: Here is the function that starts the DMA:

#define DMA_SPI_BURST_SIZE 8U

void WiznetReadRegister_DMA(Uint16 OffsetAddr, Uint16 BlockReg, Uint16 NumberReg)
{
Uint16 NumberOfTransfers;
Uint16 TxDataUDP[3];

UdpPacket.TxData[0] = OffsetAddr >> 8;
UdpPacket.TxData[0] = UdpPacket.TxData[0] << 8;
UdpPacket.TxData[1] = OffsetAddr & 0xFF;
UdpPacket.TxData[1] = UdpPacket.TxData[1] << 8;
UdpPacket.TxData[2] = (BlockReg & 0xFF) << 3;
UdpPacket.TxData[2] = UdpPacket.TxData[2] << 8;
memset((void*)&UdpPacket.TxData[3],0,NumberReg);

NumberOfTransfers = NumberReg/DMA_SPI_BURST_SIZE;

DMA_configBurst(SPIA_HW_RX_DMA_BASE, DMA_SPI_BURST_SIZE, 0, 0);
DMA_configTransfer(SPIA_HW_RX_DMA_BASE, NumberOfTransfers, 0, 0);

DMA_configBurst(SPIA_HW_TX_DMA_BASE, DMA_SPI_BURST_SIZE, 0, 0);
DMA_configTransfer(SPIA_HW_TX_DMA_BASE, NumberOfTransfers, 0, 0);

DMA_enableTrigger(SPIA_HW_TX_DMA_BASE);
DMA_startChannel(SPIA_HW_TX_DMA_BASE);
DMA_enableTrigger(SPIA_HW_RX_DMA_BASE);
DMA_startChannel(SPIA_HW_RX_DMA_BASE);

DelayUs(10);
}

0 stevenh over 1 year ago in reply to Allison Nguyen

Guru 20045 points

Ok, I still have the same issue: There is only one non-zero value in the array and the Rx FIFO still has data.

Here is the updated sysconfig file:

/**
* Write custom configuration values to the imported modules.
*/
const divider4 = system.clockTree["LOSPCP"];
divider4.divideValue = 6;

const divider5 = system.clockTree["SYSCLKDIVSEL"];
divider5.divideValue = 1;

const multiplier4 = system.clockTree["PLL_IMULT"];
multiplier4.multiplyValue = 10;

const mux8 = system.clockTree["XTAL_OR_X1"];
mux8.inputSelect = "X1";

flash1.$name = "myFMC0";
flash1.enableECC = false;

sci1.useInterrupts = false;
sci1.$name = "mySCIB";
sci1.baudRates = 38400;
sci1.sci.$assign = "SCIB";

spi1.transferProtocol = "SPI_PROT_POL0PHA1";
spi1.$name = "SPIA_HW";
spi1.mode = "SPI_MODE_CONTROLLER";
spi1.bitRate = 6666666;
spi1.dataWidth = "8";
spi1.emulationMode = "SPI_EMULATION_STOP_AFTER_TRANSMIT";
spi1.useDMARX = true;
spi1.useDMATX = true;
spi1.registerInterrupts = true;
spi1.txFifo = "SPI_FIFO_TX8";
spi1.rxFifo = "SPI_FIFO_RX4";
spi1.enabledFIFOInterrupts = ["SPI_INT_RXFF"];
spi1.useInterrupts = false;
spi1.spi.$assign = "SPIA";
spi1.spiRXDMA.databusWidthConfig = scripting.forceWrite("DMA_CFG_SIZE_16BIT");
spi1.spiRXDMA.transferSize = 16;
spi1.spiRXDMA.burstSize = 8;
spi1.spiRXDMA.destAddressInputMode = "VARIABLE";
spi1.spiRXDMA.destAddressVariable = "RxSpiDMAData";
spi1.spiRXDMA.useInterrupts = true;
spi1.spiRXDMA.registerInterrupts = true;
spi1.spiRXDMA.enableInterrupts = true;
spi1.spiRXDMA.enableTriggers = true;
spi1.spiRXDMA.interruptMode = "DMA_INT_AT_END";
spi1.spiRXDMA.emulationMode = "DMA_EMULATION_FREE_RUN";
spi1.spiRXDMA.destBurstStep = 1;
spi1.spiRXDMA.destTransferStep = 1;
spi1.spiRXDMA.srcBurstStep = 1;
spi1.spiRXDMA.srcTransferStep = 1;
spi1.spiRXDMA.dmaInt.enableInterrupt = true;
spi1.spiTXDMA.databusWidthConfig = scripting.forceWrite("DMA_CFG_SIZE_16BIT");
spi1.spiTXDMA.dmaBase = "DMA_CH2_BASE";
spi1.spiTXDMA.srcAddressInputMode = "VARIABLE";
spi1.spiTXDMA.srcAddressVariable = "TxSpiDMAData";
spi1.spiTXDMA.burstSize = 8;
spi1.spiTXDMA.transferSize = 16;
spi1.spiTXDMA.useInterrupts = true;
spi1.spiTXDMA.registerInterrupts = true;
spi1.spiTXDMA.enableInterrupts = true;
spi1.spiTXDMA.enableTriggers = true;
spi1.spiTXDMA.interruptMode = "DMA_INT_AT_END";
spi1.spiTXDMA.srcBurstStep = 1;
spi1.spiTXDMA.srcTransferStep = 1;
spi1.spiTXDMA.destBurstStep = 1;
spi1.spiTXDMA.destTransferStep = 1;
spi1.spiTXDMA.dmaInt.enableInterrupt = true;

0 stevenh over 1 year ago in reply to Allison Nguyen

Guru 20045 points

Ok, I noticed a couple of items in WiznetReadRegister_DMA() function needed to be changed (see below).

DMA_configBurst(SPIA_HW_RX_DMA_BASE, DMA_SPI_BURST_SIZE, 1, 1);
DMA_configTransfer(SPIA_HW_RX_DMA_BASE, NumberOfTransfers, 1, 1);

DMA_configBurst(SPIA_HW_TX_DMA_BASE, DMA_SPI_BURST_SIZE, 1, 1);
DMA_configTransfer(SPIA_HW_TX_DMA_BASE, NumberOfTransfers, 1, 1);

During debugging I noticed the NumberOfTransfers is set to 3 and the DMA Rx Transfer complete ISR is not called.

Also, I noticed the most of the SPIA register values are zero (see image below). I verified the processor was not resetting by putting a breakpoint on the FreeRTOS_init(); line.

After starting DMA Transfer:

Before starting DMA transfer:

0 stevenh over 1 year ago in reply to Allison Nguyen

Guru 20045 points

Ok, the clearing of the SPI register was caused by the SPI burst and transfer increment value being non-zero. I changed the settings again as shown below.

DMA_configBurst(SPIA_HW_RX_DMA_BASE, DMA_SPI_BURST_SIZE, 0, 1);
DMA_configTransfer(SPIA_HW_RX_DMA_BASE, NumberOfTransfers, 0, 1);

DMA_configBurst(SPIA_HW_TX_DMA_BASE, DMA_SPI_BURST_SIZE, 1, 0);
DMA_configTransfer(SPIA_HW_TX_DMA_BASE, NumberOfTransfers, 1, 0);

If the DMA transfer is working correct the Received data should look like the following (Starting from 0xD477. Disregard address 0xD476).

However, the DMA transfers the following data:

JFYI I changed the WiznetReadRegister_DMA code to the following.

void WiznetReadRegister_DMA(Uint16 OffsetAddr, Uint16 BlockReg, Uint16 NumberReg)
{
Uint16 TxDataUDP[3];
Uint16 Remainder;
//memset((void*)RxSpiData,0,RX_SPI_DATA_SIZE);

NumberOfTransfers = NumberReg/DMA_SPI_BURST_SIZE;

Remainder = NumberReg%DMA_SPI_BURST_SIZE;

if (Remainder)
{
NumberOfTransfers++;
}

DMA_configBurst(SPIA_HW_RX_DMA_BASE, DMA_SPI_BURST_SIZE, 0, 1);
DMA_configTransfer(SPIA_HW_RX_DMA_BASE, NumberOfTransfers, 0, 1);

DMA_configBurst(SPIA_HW_TX_DMA_BASE, DMA_SPI_BURST_SIZE, 1, 0);
DMA_configTransfer(SPIA_HW_TX_DMA_BASE, NumberOfTransfers, 1, 0);

DMA_enableTrigger(SPIA_HW_TX_DMA_BASE);
DMA_startChannel(SPIA_HW_TX_DMA_BASE);
DMA_enableTrigger(SPIA_HW_RX_DMA_BASE);
DMA_startChannel(SPIA_HW_RX_DMA_BASE);

DelayUs(10);
}

Any ideas?

0 stevenh over 1 year ago in reply to Allison Nguyen

Guru 20045 points

I enabled loopback and set the transmitted data to a known set of data (shown below). Shown below is the data received. You will notice the first burst is all zeros and the other bursts follow the data. Why would the first burst be zeros?

Know set of data:

1 2 3 20 21 22 23 24 ... 49

Received data:

0 Delaney Woodward over 1 year ago in reply to stevenh

TI__Mastermind 19395 points

Hi Steven,

This is a lot of information. Can you outline more from a high level what you are trying to achieve, and I can offer some recommendations for the DMA settings to use? From my understanding:

You are trying to use one DMA module to transfer data from a buffer in memory to the SPI TX buffer.
- How many 16-bit words are you trying to transmit in total using the SPI and how is this data laid out in memory (is it all sequential in memory?).
You are trying to use another DMA module to transfer data from the SPI RX buffer to a buffer in memory.
- How are you looking to write all of the received data into the RX memory buffer? Do you want all of the received data to be written sequentially in memory, overwritten to the same address in memory, put in different areas of memory etc.?

I can offer the recommended DMA configurations based on your use case and I believe that would be easier than trying to debug the existing issue.

Best Regards,

Delaney

0 stevenh over 1 year ago in reply to Delaney Woodward

Guru 20045 points

Hello Delaney,

W5500 Slave Rx <------------------------------ SPIA Tx <--------DMA Ch1<----------------- TxBuffer[]

W5500 Slave Tx ------------------------------->SPIA Rx -------->DMA Ch2 ----------------->RxBuffer[]

I am wanting to Read some data (8-bit data) from the W5500 using SPI and DMA as shown above.

TxBuffer[] will contain N number of bytes: the first three bytes contains information on the data that is to be retrieved from the W5500 and the rest of bytes are used to shift the data out of the W5500. RxBuffer[] will contain data with the exception that the first three bytes will have the values: 1, 2, 3.

I want the data from the W5500 to be written sequentially.

It seems to be working to a certain extent as shown in my last post with the exception that first burst contains all zeros.

DMA Burst size: 8 (8 bytes)

Transfer Size: (3+Total Data requested from W5500)/8 . This value will be rounded up.

Originally I used DMA Ch1 for SPIA Tx and DMA Ch2 for SPIA Rx. However, I reversed the two and made DMA Ch1 a high priority channel.

Stephen

+1 Delaney Woodward over 1 year ago in reply to stevenh

TI__Mastermind 19395 points

Hi Steven,

Thank you for providing an overview for me. My recommendations are the following:

TX DMA (CH2)

Burst Size = 8

Transfer Size = N / 8

Source: Burst Step = 1, Transfer Step = 1, Wrap Size = N / 8, Wrap Step = 0

Destination: Burst Step = 0, Transfer Step = 0, Wrap Size = 65535, Wrap Step = 0 (basically never wraps)

RX DMA (CH1)

Burst Size = 8

Transfer Size = N / 8

Source: Burst Step = 0, Transfer Step = 0, Wrap Size = 65535, Wrap Step = 0 (basically never wraps)

Destination: Burst Step = 1, Transfer Step = 1, Wrap Size = N / 8, Wrap Step = 0

Set both the SPI TX and RX FIFO trigger levels to 8 to match the burst size.

Make sure also to initialize the 8-bit data in the TxBuffer[] as left-shifted by 8-bits so it is received properly by the slave device, since the c28x is 16-bit addressable. For example, if trying to transmit the 8-bit value 0x01 to the slave, store the 16-bit value 0x0100 in memory. I'm assuming this should only be important for the first 3 information bytes.

stevenh said:
I want the data from the W5500 to be written sequentially.

One more clarification on this: do you want the data received to be 1) overwritten in memory (with each of the N bytes themselves written sequentially) or 2) for all received data to be written sequentially, meaning that the first N bytes received will be written at address x, then the next N bytes at address x+N, then the next at address x+N+N etc. My suggestions above are assuming option 1). I am also assuming that you will be transmitting and receiving these N bytes over and over but let me know if that is incorrect.

Best Regards,

Delaney

0 stevenh over 1 year ago in reply to Delaney Woodward

Guru 20045 points

Hello Delaney,

Thanks for the quick reply.

Why do you set Transfer Size = N/2? Shouldn't it be N/8, where 8 is the burst size and as mentioned in the Technical reference manual (TRM)?

Also, see section 5.9.3.11 of the TRM. The wrap size is the number of burst to transfer before wrapping around to the beginning, so shouldn't the wrap size also be N/8?

Here's the code I used for setting of those variables. I Also, included the Receive Buffer below for the 1st, 2nd, 3rd and 4th run of the test program. There are 4 burst, which is correct; however, the first burst is incorrect: It alternates between all zeros or some other data.

Data transmitted =

1 2 3 20 21 22 23 24 ... 49

void WiznetReadRegister_DMA(Uint16 OffsetAddr, Uint16 BlockReg, Uint16 NumberReg)
{
    Uint16 TxDataUDP[3];
    Uint16 Remainder;
    Uint16 i;
    Uint16 NumInFIFO1;
    //memset((void*)RxSpiData,0,RX_SPI_DATA_SIZE);


    UdpPacket.TxData[0] = OffsetAddr >> 8;
    UdpPacket.TxData[0] = UdpPacket.TxData[0] << 8;
    UdpPacket.TxData[1] = OffsetAddr & 0xFF;
    UdpPacket.TxData[1] = UdpPacket.TxData[1] << 8;
    UdpPacket.TxData[2] = (BlockReg & 0xFF) << 3;
    UdpPacket.TxData[2] = UdpPacket.TxData[2] << 8;
    memset((void*)&UdpPacket.TxData[3],0,NumberReg);

    NumberReg = 30;

    UdpPacket.TxData[0] = 1 << 8;
    UdpPacket.TxData[1] = 2 << 8;
    UdpPacket.TxData[2] = 3 << 8;

    for(i=0;i<30;i++)
    {
        UdpPacket.TxData[i+3] = (i+20) << 8;
    }

    NumberOfTransfers = NumberReg/8;

    Remainder = NumberReg%DMA_SPI_BURST_SIZE;

    if (Remainder)
    {
        NumberOfTransfers++;
    }

#if 1
    NumInFIFO1 = SPI_getRxFIFOStatus(SPIA_HW_BASE);

    if(NumInFIFO1)
    {
        //ReadBytes(&SPI_DATA_TEMP[0],NumInFIFO1);
    }
#endif

    //SPI_clearInterruptStatus(SPIA_HW_BASE,SPI_INT_RXFF);

    SocketInterruptStatus[0].DataReceived = 0;

    //DMA_clearTriggerFlag(SPIA_HW_RX_DMA_BASE);
    //DMA_clearTriggerFlag(SPIA_HW_TX_DMA_BASE);

    DMA_configBurst(SPIA_HW_RX_DMA_BASE, DMA_SPI_BURST_SIZE, 0, 1);
    DMA_configTransfer(SPIA_HW_RX_DMA_BASE, NumberOfTransfers, 0, 1);
    DMA_configWrap(SPIA_HW_RX_DMA_BASE, 65535U, 0, NumberOfTransfers, 0);

    DMA_configBurst(SPIA_HW_TX_DMA_BASE, DMA_SPI_BURST_SIZE, 1, 0);
    DMA_configTransfer(SPIA_HW_TX_DMA_BASE, NumberOfTransfers, 1, 0);
    DMA_configWrap(SPIA_HW_TX_DMA_BASE, NumberOfTransfers, 0, 65535U, 0);



    DMA_enableTrigger(SPIA_HW_TX_DMA_BASE);
    DMA_startChannel(SPIA_HW_TX_DMA_BASE);
    DMA_enableTrigger(SPIA_HW_RX_DMA_BASE);
    DMA_startChannel(SPIA_HW_RX_DMA_BASE);

    DelayUs(10);
}

First Run:

2nd Run

3rd Run

4th Run

0 Delaney Woodward over 1 year ago in reply to stevenh

TI__Mastermind 19395 points

Hi Steven,

Yes, sorry my mistake. I meant to write N / 8 everywhere that I have N / 2 there. Can you send what you have all of the variables set to when the output is what is shown in those screenshots? Do you have continuous or one-shot mode enabled?

Another note: sometimes setting breakpoints in the end of transfer DMA interrupts can cause issues that wouldn't otherwise exist. For testing purposes, you could instead add a counter to the interrupts and ESTOP in the main when the counter reaches a certain value and then check the state of the memory then. Not sure if this is what you were doing but just wanted to mention it.

Best Regards,

Delaney

0 stevenh over 1 year ago in reply to Delaney Woodward

Guru 20045 points

Hello delaney,

The transfer occurs correctly the first time the program runs. However, on subsequent runs it is not transferring correctly (see Rx Buffer and Registers below for 1st and 2nd run).

I also included some code at the bottom of this message. Also, updated the system config file in case I updated anything.

I no-longer put a breakpoint in the DMA SPI Rx transfer complete ISR.

Registers before starting transfer for 1st run:

DmaClaSrcSelRegs DMA CLA SRC SEL Registers
CLA1TASKSRCSELLOCK 0x00000000 CLA1 Task Trigger Source Select Lock Register [Memory Mapped]
DMACHSRCSELLOCK 0x00000000 DMA Channel Triger Source Select Lock Register [Memory Mapped]
CLA1TASKSRCSEL1 0x00000000 CLA1 Task Trigger Source Select Register-1 [Memory Mapped]
CLA1TASKSRCSEL2 0x00000000 CLA1 Task Trigger Source Select Register-2 [Memory Mapped]
DMACHSRCSEL1 0x00006E6D DMA Channel Trigger Source Select Register-1 [Memory Mapped]
DMACHSRCSEL2 0x00000000 DMA Channel Trigger Source Select Register-2 [Memory Mapped]
DmaRegs DMA Registers
DMACTRL 0x0000 DMA Control Register [Memory Mapped]
DEBUGCTRL 0x0000 Debug Control Register [Memory Mapped]
PRIORITYCTRL1 0x0001 Priority Control 1 Register [Memory Mapped]
PRIORITYSTAT 0x0000 Priority Status Register [Memory Mapped]
DmaCh1Regs DMA CH Registers
MODE 0x8301 Mode Register [Memory Mapped]
CHINTE 1 Channel Interrupt Enable Bit
DATASIZE 0 Data Size Mode Bit
CONTINUOUS 0 Continuous Mode Bit
ONESHOT 0 One Shot Mode Bit
CHINTMODE 1 Channel Interrupt Mode
PERINTE 1 Peripheral Interrupt Enable
OVRINTE 0 Overflow Interrupt Enable
PERINTSEL 00001 Peripheral Interrupt and Sync Select
CONTROL 0x0100 Control Register [Memory Mapped]
OVRFLG 0 Overflow Flag Bit
RUNSTS 0 Run Status Bit
BURSTSTS 0 Burst Status Bit
TRANSFERSTS 0 Transfer Status Bit
PERINTFLG 1 Interrupt Flag Bit
ERRCLR 0 Error Clear Bit
PERINTCLR 0 Interrupt Clear Bit
PERINTFRC 0 Interrupt Force Bit
SOFTRESET 0 Soft Reset Bit
HALT 0 Halt Bit
RUN 0 Run Bit
BURST_SIZE 0x0007 Burst Size Register [Memory Mapped]
BURST_COUNT 0x0000 Burst Count Register [Memory Mapped]
SRC_BURST_STEP 0x0001 Source Burst Step Register [Memory Mapped]
DST_BURST_STEP 0x0000 Destination Burst Step Register [Memory Mapped]
TRANSFER_SIZE 0x0003 Transfer Size Register [Memory Mapped]
TRANSFER_COUNT 0x0000 Transfer Count Register [Memory Mapped]
SRC_TRANSFER_STEP 0x0001 Source Transfer Step Register [Memory Mapped]
DST_TRANSFER_STEP 0x0000 Destination Transfer Step Register [Memory Mapped]
SRC_WRAP_SIZE 0x0003 Source Wrap Size Register [Memory Mapped]
SRC_WRAP_COUNT 0x0000 Source Wrap Count Register [Memory Mapped]
SRC_WRAP_STEP 0x0000 Source Wrap Step Register [Memory Mapped]
DST_WRAP_SIZE 0xFFFE Destination Wrap Size Register [Memory Mapped]
DST_WRAP_COUNT 0x0000 Destination Wrap Count Register [Memory Mapped]
DST_WRAP_STEP 0x0000 Destination Wrap Step Register [Memory Mapped]
SRC_BEG_ADDR_SHADOW 0x0000C270 Source Begin Address Shadow Register [Memory Mapped]
SRC_ADDR_SHADOW 0x0000C270 Source Address Shadow Register [Memory Mapped]
SRC_BEG_ADDR_ACTIVE 0x00000000 Source Begin Address Active Register [Memory Mapped]
SRC_ADDR_ACTIVE 0x00000000 Source Address Active Register [Memory Mapped]
DST_BEG_ADDR_SHADOW 0x00006108 Destination Begin Address Shadow Register [Memory Mapped]
DST_ADDR_SHADOW 0x00006108 Destination Address Shadow Register [Memory Mapped]
DST_BEG_ADDR_ACTIVE 0x00000000 Destination Begin Address Active Register [Memory Mapped]
DST_ADDR_ACTIVE 0x00000000 Destination Address Active Register [Memory Mapped]
DmaCh2Regs DMA CH Registers
MODE 0x8302 Mode Register [Memory Mapped]
CHINTE 1 Channel Interrupt Enable Bit
DATASIZE 0 Data Size Mode Bit
CONTINUOUS 0 Continuous Mode Bit
ONESHOT 0 One Shot Mode Bit
CHINTMODE 1 Channel Interrupt Mode
PERINTE 1 Peripheral Interrupt Enable
OVRINTE 0 Overflow Interrupt Enable
PERINTSEL 00010 Peripheral Interrupt and Sync Select
CONTROL 0x0000 Control Register [Memory Mapped]
OVRFLG 0 Overflow Flag Bit
RUNSTS 0 Run Status Bit
BURSTSTS 0 Burst Status Bit
TRANSFERSTS 0 Transfer Status Bit
PERINTFLG 0 Interrupt Flag Bit
ERRCLR 0 Error Clear Bit
PERINTCLR 0 Interrupt Clear Bit
PERINTFRC 0 Interrupt Force Bit
SOFTRESET 0 Soft Reset Bit
HALT 0 Halt Bit
RUN 0 Run Bit
BURST_SIZE 0x0007 Burst Size Register [Memory Mapped]
BURST_COUNT 0x0000 Burst Count Register [Memory Mapped]
SRC_BURST_STEP 0x0000 Source Burst Step Register [Memory Mapped]
DST_BURST_STEP 0x0001 Destination Burst Step Register [Memory Mapped]
TRANSFER_SIZE 0x0003 Transfer Size Register [Memory Mapped]
TRANSFER_COUNT 0x0000 Transfer Count Register [Memory Mapped]
SRC_TRANSFER_STEP 0x0000 Source Transfer Step Register [Memory Mapped]
DST_TRANSFER_STEP 0x0001 Destination Transfer Step Register [Memory Mapped]
SRC_WRAP_SIZE 0xFFFE Source Wrap Size Register [Memory Mapped]
SRC_WRAP_COUNT 0x0000 Source Wrap Count Register [Memory Mapped]
SRC_WRAP_STEP 0x0000 Source Wrap Step Register [Memory Mapped]
DST_WRAP_SIZE 0x0003 Destination Wrap Size Register [Memory Mapped]
DST_WRAP_COUNT 0x0000 Destination Wrap Count Register [Memory Mapped]
DST_WRAP_STEP 0x0000 Destination Wrap Step Register [Memory Mapped]
SRC_BEG_ADDR_SHADOW 0x00006107 Source Begin Address Shadow Register [Memory Mapped]
SRC_ADDR_SHADOW 0x00006107 Source Address Shadow Register [Memory Mapped]
SRC_BEG_ADDR_ACTIVE 0x00000000 Source Begin Address Active Register [Memory Mapped]
SRC_ADDR_ACTIVE 0x00000000 Source Address Active Register [Memory Mapped]
DST_BEG_ADDR_SHADOW 0x0000CB70 Destination Begin Address Shadow Register [Memory Mapped]
DST_ADDR_SHADOW 0x0000CB70 Destination Address Shadow Register [Memory Mapped]
DST_BEG_ADDR_ACTIVE 0x00000000 Destination Begin Address Active Register [Memory Mapped]
DST_ADDR_ACTIVE 0x00000000 Destination Address Active Register [Memory Mapped]
SpiaRegs SPI Registers
SPICCR 0x0097 SPI Configuration Control Register [Memory Mapped]
SPISWRESET 1 SPI Software Reset
CLKPOLARITY 0 Shift Clock Polarity
HS_MODE 0 High Speed mode control
SPILBK 1 SPI Loopback
SPICHAR 0111 Character Length Control
SPICTL 0x000E SPI Operation Control Register [Memory Mapped]
OVERRUNINTENA 0 Overrun Interrupt Enable
CLK_PHASE 1 SPI Clock Phase
MASTER_SLAVE 1 SPI Network Mode Control
TALK 1 Master/Slave Transmit Enable
SPIINTENA 0 SPI Interupt Enable
SPISTS 0x0000 SPI Status Register [Memory Mapped]
OVERRUN_FLAG * SPI Receiver Overrun Flag
INT_FLAG 0 SPI Interrupt Flag
BUFFULL_FLAG 0 SPI Transmit Buffer Full Flag
SPIBRR 0x0004 SPI Baud Rate Register [Memory Mapped]
SPI_BIT_RATE 0000100 SPI Bit Rate Control
SPIRXEMU 0x0004 SPI Emulation Buffer Register [Memory Mapped]
SPIRXBUF 0x0000 SPI Serial Input Buffer Register [Memory Mapped]
SPITXBUF 0x0400 SPI Serial Output Buffer Register [Memory Mapped]
SPIDAT 0x0004 SPI Serial Data Register [Memory Mapped]
SPIFFTX 0xE088 SPI FIFO Transmit Register [Memory Mapped]
SPIRST 1 SPI Reset
SPIFFENA 1 FIFO Enhancements Enable
TXFIFO 1 TXFIFO Reset
TXFFST 00000 Transmit FIFO Status
TXFFINT 1 TXFIFO Interrupt Flag
TXFFINTCLR * TXFIFO Interrupt Clear
TXFFIENA 0 TXFIFO Interrupt Enable
TXFFIL 01000 TXFIFO Interrupt Level
SPIFFRX 0x2008 SPI FIFO Receive Register [Memory Mapped]
RXFFOVF 0 Receive FIFO Overflow Flag
RXFFOVFCLR * Receive FIFO Overflow Clear
RXFIFORESET 1 RXFIFO Reset
RXFFST 00000 Receive FIFO Status
RXFFINT 0 RXFIFO Interrupt Flag
RXFFINTCLR * RXFIFO Interupt Clear
RXFFIENA 0 RXFIFO Interrupt Enable
RXFFIL 01000 RXFIFO Interrupt Level
SPIFFCT 0x0000 SPI FIFO Control Register [Memory Mapped]
TXDLY 00000000 FIFO Transmit Delay Bits
SPIPRI 0x0020 SPI Priority Control Register [Memory Mapped]

Rx Buffer after the 1s run:

Registers after first run:

DmaClaSrcSelRegs DMA CLA SRC SEL Registers
CLA1TASKSRCSELLOCK 0x00000000 CLA1 Task Trigger Source Select Lock Register [Memory Mapped]
DMACHSRCSELLOCK 0x00000000 DMA Channel Triger Source Select Lock Register [Memory Mapped]
CLA1TASKSRCSEL1 0x00000000 CLA1 Task Trigger Source Select Register-1 [Memory Mapped]
CLA1TASKSRCSEL2 0x00000000 CLA1 Task Trigger Source Select Register-2 [Memory Mapped]
DMACHSRCSEL1 0x00006E6D DMA Channel Trigger Source Select Register-1 [Memory Mapped]
DMACHSRCSEL2 0x00000000 DMA Channel Trigger Source Select Register-2 [Memory Mapped]
DmaRegs DMA Registers
DMACTRL 0x0000 DMA Control Register [Memory Mapped]
DEBUGCTRL 0x0000 Debug Control Register [Memory Mapped]
PRIORITYCTRL1 0x0001 Priority Control 1 Register [Memory Mapped]
PRIORITYSTAT 0x0000 Priority Status Register [Memory Mapped]
DmaCh1Regs DMA CH Registers
MODE 0x8301 Mode Register [Memory Mapped]
CHINTE 1 Channel Interrupt Enable Bit
DATASIZE 0 Data Size Mode Bit
CONTINUOUS 0 Continuous Mode Bit
ONESHOT 0 One Shot Mode Bit
CHINTMODE 1 Channel Interrupt Mode
PERINTE 1 Peripheral Interrupt Enable
OVRINTE 0 Overflow Interrupt Enable
PERINTSEL 00001 Peripheral Interrupt and Sync Select
CONTROL 0x0100 Control Register [Memory Mapped]
OVRFLG 0 Overflow Flag Bit
RUNSTS 0 Run Status Bit
BURSTSTS 0 Burst Status Bit
TRANSFERSTS 0 Transfer Status Bit
PERINTFLG 1 Interrupt Flag Bit
ERRCLR 0 Error Clear Bit
PERINTCLR 0 Interrupt Clear Bit
PERINTFRC 0 Interrupt Force Bit
SOFTRESET 0 Soft Reset Bit
HALT 0 Halt Bit
RUN 0 Run Bit
BURST_SIZE 0x0007 Burst Size Register [Memory Mapped]
BURST_COUNT 0x0000 Burst Count Register [Memory Mapped]
SRC_BURST_STEP 0x0001 Source Burst Step Register [Memory Mapped]
DST_BURST_STEP 0x0000 Destination Burst Step Register [Memory Mapped]
TRANSFER_SIZE 0x0003 Transfer Size Register [Memory Mapped]
TRANSFER_COUNT 0x0000 Transfer Count Register [Memory Mapped]
SRC_TRANSFER_STEP 0x0001 Source Transfer Step Register [Memory Mapped]
DST_TRANSFER_STEP 0x0000 Destination Transfer Step Register [Memory Mapped]
SRC_WRAP_SIZE 0x0003 Source Wrap Size Register [Memory Mapped]
SRC_WRAP_COUNT 0x0003 Source Wrap Count Register [Memory Mapped]
SRC_WRAP_STEP 0x0000 Source Wrap Step Register [Memory Mapped]
DST_WRAP_SIZE 0xFFFE Destination Wrap Size Register [Memory Mapped]
DST_WRAP_COUNT 0xFFFA Destination Wrap Count Register [Memory Mapped]
DST_WRAP_STEP 0x0000 Destination Wrap Step Register [Memory Mapped]
SRC_BEG_ADDR_SHADOW 0x0000C270 Source Begin Address Shadow Register [Memory Mapped]
SRC_ADDR_SHADOW 0x0000C270 Source Address Shadow Register [Memory Mapped]
SRC_BEG_ADDR_ACTIVE 0x0000C270 Source Begin Address Active Register [Memory Mapped]
SRC_ADDR_ACTIVE 0x0000C270 Source Address Active Register [Memory Mapped]
DST_BEG_ADDR_SHADOW 0x00006108 Destination Begin Address Shadow Register [Memory Mapped]
DST_ADDR_SHADOW 0x00006108 Destination Address Shadow Register [Memory Mapped]
DST_BEG_ADDR_ACTIVE 0x00006108 Destination Begin Address Active Register [Memory Mapped]
DST_ADDR_ACTIVE 0x00006108 Destination Address Active Register [Memory Mapped]
DmaCh2Regs DMA CH Registers
MODE 0x8302 Mode Register [Memory Mapped]
CHINTE 1 Channel Interrupt Enable Bit
DATASIZE 0 Data Size Mode Bit
CONTINUOUS 0 Continuous Mode Bit
ONESHOT 0 One Shot Mode Bit
CHINTMODE 1 Channel Interrupt Mode
PERINTE 1 Peripheral Interrupt Enable
OVRINTE 0 Overflow Interrupt Enable
PERINTSEL 00010 Peripheral Interrupt and Sync Select
CONTROL 0x0100 Control Register [Memory Mapped]
OVRFLG 0 Overflow Flag Bit
RUNSTS 0 Run Status Bit
BURSTSTS 0 Burst Status Bit
TRANSFERSTS 0 Transfer Status Bit
PERINTFLG 1 Interrupt Flag Bit
ERRCLR 0 Error Clear Bit
PERINTCLR 0 Interrupt Clear Bit
PERINTFRC 0 Interrupt Force Bit
SOFTRESET 0 Soft Reset Bit
HALT 0 Halt Bit
RUN 0 Run Bit
BURST_SIZE 0x0007 Burst Size Register [Memory Mapped]
BURST_COUNT 0x0000 Burst Count Register [Memory Mapped]
SRC_BURST_STEP 0x0000 Source Burst Step Register [Memory Mapped]
DST_BURST_STEP 0x0001 Destination Burst Step Register [Memory Mapped]
TRANSFER_SIZE 0x0003 Transfer Size Register [Memory Mapped]
TRANSFER_COUNT 0x0000 Transfer Count Register [Memory Mapped]
SRC_TRANSFER_STEP 0x0000 Source Transfer Step Register [Memory Mapped]
DST_TRANSFER_STEP 0x0001 Destination Transfer Step Register [Memory Mapped]
SRC_WRAP_SIZE 0xFFFE Source Wrap Size Register [Memory Mapped]
SRC_WRAP_COUNT 0xFFFA Source Wrap Count Register [Memory Mapped]
SRC_WRAP_STEP 0x0000 Source Wrap Step Register [Memory Mapped]
DST_WRAP_SIZE 0x0003 Destination Wrap Size Register [Memory Mapped]
DST_WRAP_COUNT 0x0003 Destination Wrap Count Register [Memory Mapped]
DST_WRAP_STEP 0x0000 Destination Wrap Step Register [Memory Mapped]
SRC_BEG_ADDR_SHADOW 0x00006107 Source Begin Address Shadow Register [Memory Mapped]
SRC_ADDR_SHADOW 0x00006107 Source Address Shadow Register [Memory Mapped]
SRC_BEG_ADDR_ACTIVE 0x00006107 Source Begin Address Active Register [Memory Mapped]
SRC_ADDR_ACTIVE 0x00006107 Source Address Active Register [Memory Mapped]
DST_BEG_ADDR_SHADOW 0x0000CB70 Destination Begin Address Shadow Register [Memory Mapped]
DST_ADDR_SHADOW 0x0000CB70 Destination Address Shadow Register [Memory Mapped]
DST_BEG_ADDR_ACTIVE 0x0000CB70 Destination Begin Address Active Register [Memory Mapped]
DST_ADDR_ACTIVE 0x0000CB70 Destination Address Active Register [Memory Mapped]
SpiaRegs SPI Registers
SPICCR 0x0097 SPI Configuration Control Register [Memory Mapped]
SPISWRESET 1 SPI Software Reset
CLKPOLARITY 0 Shift Clock Polarity
HS_MODE 0 High Speed mode control
SPILBK 1 SPI Loopback
SPICHAR 0111 Character Length Control
SPICTL 0x000E SPI Operation Control Register [Memory Mapped]
OVERRUNINTENA 0 Overrun Interrupt Enable
CLK_PHASE 1 SPI Clock Phase
MASTER_SLAVE 1 SPI Network Mode Control
TALK 1 Master/Slave Transmit Enable
SPIINTENA 0 SPI Interupt Enable
SPISTS 0x0000 SPI Status Register [Memory Mapped]
OVERRUN_FLAG * SPI Receiver Overrun Flag
INT_FLAG 0 SPI Interrupt Flag
BUFFULL_FLAG 0 SPI Transmit Buffer Full Flag
SPIBRR 0x0004 SPI Baud Rate Register [Memory Mapped]
SPI_BIT_RATE 0000100 SPI Bit Rate Control
SPIRXEMU 0x0001 SPI Emulation Buffer Register [Memory Mapped]
SPIRXBUF 0x0000 SPI Serial Input Buffer Register [Memory Mapped]
SPITXBUF 0x0100 SPI Serial Output Buffer Register [Memory Mapped]
SPIDAT 0x0001 SPI Serial Data Register [Memory Mapped]
SPIFFTX 0xE088 SPI FIFO Transmit Register [Memory Mapped]
SPIRST 1 SPI Reset
SPIFFENA 1 FIFO Enhancements Enable
TXFIFO 1 TXFIFO Reset
TXFFST 00000 Transmit FIFO Status
TXFFINT 1 TXFIFO Interrupt Flag
TXFFINTCLR * TXFIFO Interrupt Clear
TXFFIENA 0 TXFIFO Interrupt Enable
TXFFIL 01000 TXFIFO Interrupt Level
SPIFFRX 0x2008 SPI FIFO Receive Register [Memory Mapped]
RXFFOVF 0 Receive FIFO Overflow Flag
RXFFOVFCLR * Receive FIFO Overflow Clear
RXFIFORESET 1 RXFIFO Reset
RXFFST 00000 Receive FIFO Status
RXFFINT 0 RXFIFO Interrupt Flag
RXFFINTCLR * RXFIFO Interupt Clear
RXFFIENA 0 RXFIFO Interrupt Enable
RXFFIL 01000 RXFIFO Interrupt Level
SPIFFCT 0x0000 SPI FIFO Control Register [Memory Mapped]
TXDLY 00000000 FIFO Transmit Delay Bits
SPIPRI 0x0020 SPI Priority Control Register [Memory Mapped]

Registers before 2nd run (same breakpoint as before 1st run):

DmaClaSrcSelRegs DMA CLA SRC SEL Registers
CLA1TASKSRCSELLOCK 0x00000000 CLA1 Task Trigger Source Select Lock Register [Memory Mapped]
DMACHSRCSELLOCK 0x00000000 DMA Channel Triger Source Select Lock Register [Memory Mapped]
CLA1TASKSRCSEL1 0x00000000 CLA1 Task Trigger Source Select Register-1 [Memory Mapped]
CLA1TASKSRCSEL2 0x00000000 CLA1 Task Trigger Source Select Register-2 [Memory Mapped]
DMACHSRCSEL1 0x00006E6D DMA Channel Trigger Source Select Register-1 [Memory Mapped]
DMACHSRCSEL2 0x00000000 DMA Channel Trigger Source Select Register-2 [Memory Mapped]
DmaRegs DMA Registers
DMACTRL 0x0000 DMA Control Register [Memory Mapped]
DEBUGCTRL 0x0000 Debug Control Register [Memory Mapped]
PRIORITYCTRL1 0x0001 Priority Control 1 Register [Memory Mapped]
PRIORITYSTAT 0x0000 Priority Status Register [Memory Mapped]
DmaCh1Regs DMA CH Registers
MODE 0x8301 Mode Register [Memory Mapped]
CHINTE 1 Channel Interrupt Enable Bit
DATASIZE 0 Data Size Mode Bit
CONTINUOUS 0 Continuous Mode Bit
ONESHOT 0 One Shot Mode Bit
CHINTMODE 1 Channel Interrupt Mode
PERINTE 1 Peripheral Interrupt Enable
OVRINTE 0 Overflow Interrupt Enable
PERINTSEL 00001 Peripheral Interrupt and Sync Select
CONTROL 0x0100 Control Register [Memory Mapped]
OVRFLG 0 Overflow Flag Bit
RUNSTS 0 Run Status Bit
BURSTSTS 0 Burst Status Bit
TRANSFERSTS 0 Transfer Status Bit
PERINTFLG 1 Interrupt Flag Bit
ERRCLR 0 Error Clear Bit
PERINTCLR 0 Interrupt Clear Bit
PERINTFRC 0 Interrupt Force Bit
SOFTRESET 0 Soft Reset Bit
HALT 0 Halt Bit
RUN 0 Run Bit
BURST_SIZE 0x0007 Burst Size Register [Memory Mapped]
BURST_COUNT 0x0000 Burst Count Register [Memory Mapped]
SRC_BURST_STEP 0x0001 Source Burst Step Register [Memory Mapped]
DST_BURST_STEP 0x0000 Destination Burst Step Register [Memory Mapped]
TRANSFER_SIZE 0x0003 Transfer Size Register [Memory Mapped]
TRANSFER_COUNT 0x0000 Transfer Count Register [Memory Mapped]
SRC_TRANSFER_STEP 0x0001 Source Transfer Step Register [Memory Mapped]
DST_TRANSFER_STEP 0x0000 Destination Transfer Step Register [Memory Mapped]
SRC_WRAP_SIZE 0x0003 Source Wrap Size Register [Memory Mapped]
SRC_WRAP_COUNT 0x0003 Source Wrap Count Register [Memory Mapped]
SRC_WRAP_STEP 0x0000 Source Wrap Step Register [Memory Mapped]
DST_WRAP_SIZE 0xFFFE Destination Wrap Size Register [Memory Mapped]
DST_WRAP_COUNT 0xFFFA Destination Wrap Count Register [Memory Mapped]
DST_WRAP_STEP 0x0000 Destination Wrap Step Register [Memory Mapped]
SRC_BEG_ADDR_SHADOW 0x0000C270 Source Begin Address Shadow Register [Memory Mapped]
SRC_ADDR_SHADOW 0x0000C270 Source Address Shadow Register [Memory Mapped]
SRC_BEG_ADDR_ACTIVE 0x0000C270 Source Begin Address Active Register [Memory Mapped]
SRC_ADDR_ACTIVE 0x0000C270 Source Address Active Register [Memory Mapped]
DST_BEG_ADDR_SHADOW 0x00006108 Destination Begin Address Shadow Register [Memory Mapped]
DST_ADDR_SHADOW 0x00006108 Destination Address Shadow Register [Memory Mapped]
DST_BEG_ADDR_ACTIVE 0x00006108 Destination Begin Address Active Register [Memory Mapped]
DST_ADDR_ACTIVE 0x00006108 Destination Address Active Register [Memory Mapped]
DmaCh2Regs DMA CH Registers
MODE 0x8302 Mode Register [Memory Mapped]
CHINTE 1 Channel Interrupt Enable Bit
DATASIZE 0 Data Size Mode Bit
CONTINUOUS 0 Continuous Mode Bit
ONESHOT 0 One Shot Mode Bit
CHINTMODE 1 Channel Interrupt Mode
PERINTE 1 Peripheral Interrupt Enable
OVRINTE 0 Overflow Interrupt Enable
PERINTSEL 00010 Peripheral Interrupt and Sync Select
CONTROL 0x0100 Control Register [Memory Mapped]
OVRFLG 0 Overflow Flag Bit
RUNSTS 0 Run Status Bit
BURSTSTS 0 Burst Status Bit
TRANSFERSTS 0 Transfer Status Bit
PERINTFLG 1 Interrupt Flag Bit
ERRCLR 0 Error Clear Bit
PERINTCLR 0 Interrupt Clear Bit
PERINTFRC 0 Interrupt Force Bit
SOFTRESET 0 Soft Reset Bit
HALT 0 Halt Bit
RUN 0 Run Bit
BURST_SIZE 0x0007 Burst Size Register [Memory Mapped]
BURST_COUNT 0x0000 Burst Count Register [Memory Mapped]
SRC_BURST_STEP 0x0000 Source Burst Step Register [Memory Mapped]
DST_BURST_STEP 0x0001 Destination Burst Step Register [Memory Mapped]
TRANSFER_SIZE 0x0003 Transfer Size Register [Memory Mapped]
TRANSFER_COUNT 0x0000 Transfer Count Register [Memory Mapped]
SRC_TRANSFER_STEP 0x0000 Source Transfer Step Register [Memory Mapped]
DST_TRANSFER_STEP 0x0001 Destination Transfer Step Register [Memory Mapped]
SRC_WRAP_SIZE 0xFFFE Source Wrap Size Register [Memory Mapped]
SRC_WRAP_COUNT 0xFFFA Source Wrap Count Register [Memory Mapped]
SRC_WRAP_STEP 0x0000 Source Wrap Step Register [Memory Mapped]
DST_WRAP_SIZE 0x0003 Destination Wrap Size Register [Memory Mapped]
DST_WRAP_COUNT 0x0003 Destination Wrap Count Register [Memory Mapped]
DST_WRAP_STEP 0x0000 Destination Wrap Step Register [Memory Mapped]
SRC_BEG_ADDR_SHADOW 0x00006107 Source Begin Address Shadow Register [Memory Mapped]
SRC_ADDR_SHADOW 0x00006107 Source Address Shadow Register [Memory Mapped]
SRC_BEG_ADDR_ACTIVE 0x00006107 Source Begin Address Active Register [Memory Mapped]
SRC_ADDR_ACTIVE 0x00006107 Source Address Active Register [Memory Mapped]
DST_BEG_ADDR_SHADOW 0x0000CB70 Destination Begin Address Shadow Register [Memory Mapped]
DST_ADDR_SHADOW 0x0000CB70 Destination Address Shadow Register [Memory Mapped]
DST_BEG_ADDR_ACTIVE 0x0000CB70 Destination Begin Address Active Register [Memory Mapped]
DST_ADDR_ACTIVE 0x0000CB70 Destination Address Active Register [Memory Mapped]
SpiaRegs SPI Registers
SPICCR 0x0097 SPI Configuration Control Register [Memory Mapped]
SPISWRESET 1 SPI Software Reset
CLKPOLARITY 0 Shift Clock Polarity
HS_MODE 0 High Speed mode control
SPILBK 1 SPI Loopback
SPICHAR 0111 Character Length Control
SPICTL 0x000E SPI Operation Control Register [Memory Mapped]
OVERRUNINTENA 0 Overrun Interrupt Enable
CLK_PHASE 1 SPI Clock Phase
MASTER_SLAVE 1 SPI Network Mode Control
TALK 1 Master/Slave Transmit Enable
SPIINTENA 0 SPI Interupt Enable
SPISTS 0x0000 SPI Status Register [Memory Mapped]
OVERRUN_FLAG * SPI Receiver Overrun Flag
INT_FLAG 0 SPI Interrupt Flag
BUFFULL_FLAG 0 SPI Transmit Buffer Full Flag
SPIBRR 0x0004 SPI Baud Rate Register [Memory Mapped]
SPI_BIT_RATE 0000100 SPI Bit Rate Control
SPIRXEMU 0x0004 SPI Emulation Buffer Register [Memory Mapped]
SPIRXBUF 0x0000 SPI Serial Input Buffer Register [Memory Mapped]
SPITXBUF 0x0400 SPI Serial Output Buffer Register [Memory Mapped]
SPIDAT 0x0004 SPI Serial Data Register [Memory Mapped]
SPIFFTX 0xE088 SPI FIFO Transmit Register [Memory Mapped]
SPIRST 1 SPI Reset
SPIFFENA 1 FIFO Enhancements Enable
TXFIFO 1 TXFIFO Reset
TXFFST 00000 Transmit FIFO Status
TXFFINT 1 TXFIFO Interrupt Flag
TXFFINTCLR * TXFIFO Interrupt Clear
TXFFIENA 0 TXFIFO Interrupt Enable
TXFFIL 01000 TXFIFO Interrupt Level
SPIFFRX 0x2008 SPI FIFO Receive Register [Memory Mapped]
RXFFOVF 0 Receive FIFO Overflow Flag
RXFFOVFCLR * Receive FIFO Overflow Clear
RXFIFORESET 1 RXFIFO Reset
RXFFST 00000 Receive FIFO Status
RXFFINT 0 RXFIFO Interrupt Flag
RXFFINTCLR * RXFIFO Interupt Clear
RXFFIENA 0 RXFIFO Interrupt Enable
RXFFIL 01000 RXFIFO Interrupt Level
SPIFFCT 0x0000 SPI FIFO Control Register [Memory Mapped]
TXDLY 00000000 FIFO Transmit Delay Bits
SPIPRI 0x0020 SPI Priority Control Register [Memory Mapped]

Rx Buffer after 2nd Run:

Registers after 2nd Run:
SpiaRegs SPI Registers
SPICCR 0x0097 SPI Configuration Control Register [Memory Mapped]
SPISWRESET 1 SPI Software Reset
CLKPOLARITY 0 Shift Clock Polarity
HS_MODE 0 High Speed mode control
SPILBK 1 SPI Loopback
SPICHAR 0111 Character Length Control
SPICTL 0x000E SPI Operation Control Register [Memory Mapped]
OVERRUNINTENA 0 Overrun Interrupt Enable
CLK_PHASE 1 SPI Clock Phase
MASTER_SLAVE 1 SPI Network Mode Control
TALK 1 Master/Slave Transmit Enable
SPIINTENA 0 SPI Interupt Enable
SPISTS 0x0000 SPI Status Register [Memory Mapped]
OVERRUN_FLAG * SPI Receiver Overrun Flag
INT_FLAG 0 SPI Interrupt Flag
BUFFULL_FLAG 0 SPI Transmit Buffer Full Flag
SPIBRR 0x0004 SPI Baud Rate Register [Memory Mapped]
SPI_BIT_RATE 0000100 SPI Bit Rate Control
SPIRXEMU 0x0001 SPI Emulation Buffer Register [Memory Mapped]
SPIRXBUF 0x0000 SPI Serial Input Buffer Register [Memory Mapped]
SPITXBUF 0x0100 SPI Serial Output Buffer Register [Memory Mapped]
SPIDAT 0x0001 SPI Serial Data Register [Memory Mapped]
SPIFFTX 0xE088 SPI FIFO Transmit Register [Memory Mapped]
SPIRST 1 SPI Reset
SPIFFENA 1 FIFO Enhancements Enable
TXFIFO 1 TXFIFO Reset
TXFFST 00000 Transmit FIFO Status
TXFFINT 1 TXFIFO Interrupt Flag
TXFFINTCLR * TXFIFO Interrupt Clear
TXFFIENA 0 TXFIFO Interrupt Enable
TXFFIL 01000 TXFIFO Interrupt Level
SPIFFRX 0x2888 SPI FIFO Receive Register [Memory Mapped]
RXFFOVF 0 Receive FIFO Overflow Flag
RXFFOVFCLR * Receive FIFO Overflow Clear
RXFIFORESET 1 RXFIFO Reset
RXFFST 01000 Receive FIFO Status
RXFFINT 1 RXFIFO Interrupt Flag
RXFFINTCLR * RXFIFO Interupt Clear
RXFFIENA 0 RXFIFO Interrupt Enable
RXFFIL 01000 RXFIFO Interrupt Level
SPIFFCT 0x0000 SPI FIFO Control Register [Memory Mapped]
TXDLY 00000000 FIFO Transmit Delay Bits
SPIPRI 0x0020 SPI Priority Control Register [Memory Mapped]

#define DMA_SPI_BURST_SIZE  8U
Uint16 NumberOfTransfers;

Uint16 SPI_DATA_TEMP[16];

void WiznetReadRegister_DMA(Uint16 OffsetAddr, Uint16 BlockReg, Uint16 NumberReg)
{
    Uint16 TxDataUDP[3];
    Uint16 Remainder;
    Uint16 i;
    Uint16 NumInFIFO1;
    //memset((void*)RxSpiData,0,RX_SPI_DATA_SIZE);


    UdpPacket.TxData[0] = OffsetAddr >> 8;
    UdpPacket.TxData[0] = UdpPacket.TxData[0] << 8;
    UdpPacket.TxData[1] = OffsetAddr & 0xFF;
    UdpPacket.TxData[1] = UdpPacket.TxData[1] << 8;
    UdpPacket.TxData[2] = (BlockReg & 0xFF) << 3;
    UdpPacket.TxData[2] = UdpPacket.TxData[2] << 8;
    memset((void*)&UdpPacket.TxData[3],0,NumberReg);

    NumberReg = 30;

    UdpPacket.TxData[0] = 1 << 8;
    UdpPacket.TxData[1] = 2 << 8;
    UdpPacket.TxData[2] = 3 << 8;

    for(i=0;i<30;i++)
    {
        UdpPacket.TxData[i+3] = (i+20) << 8;
    }

    NumberOfTransfers = NumberReg/8;

    Remainder = NumberReg%DMA_SPI_BURST_SIZE;

    if (Remainder)
    {
        NumberOfTransfers++;
    }

#if 1
    NumInFIFO1 = SPI_getRxFIFOStatus(SPIA_HW_BASE);

    if(NumInFIFO1)
    {
        ReadBytes(&SPI_DATA_TEMP[0],NumInFIFO1);
    }
#endif

    SPI_setFIFOInterruptLevel(SPIA_HW_BASE, SPI_FIFO_TX8, SPI_FIFO_RX8);

    //SPI_clearInterruptStatus(SPIA_HW_BASE,SPI_INT_RXFF);

    SPI_clearInterruptStatus(SPIA_HW_BASE,SPI_INT_RXFF);
    SPI_clearInterruptStatus(SPIA_HW_BASE,SPI_INT_TXFF);

    //DMA_clearTriggerFlag(SPIA_HW_RX_DMA_BASE);
    //DMA_clearTriggerFlag(SPIA_HW_TX_DMA_BASE);

    SocketInterruptStatus[0].DataReceived = 0;

DINT;

    DMA_configBurst(SPIA_HW_RX_DMA_BASE, DMA_SPI_BURST_SIZE, 0, 1);
    DMA_configTransfer(SPIA_HW_RX_DMA_BASE, NumberOfTransfers, 0, 1);
    DMA_configWrap(SPIA_HW_RX_DMA_BASE, 65535U, 0, NumberOfTransfers, 0);

    DMA_configBurst(SPIA_HW_TX_DMA_BASE, DMA_SPI_BURST_SIZE, 1, 0);
    DMA_configTransfer(SPIA_HW_TX_DMA_BASE, NumberOfTransfers, 1, 0);
    DMA_configWrap(SPIA_HW_TX_DMA_BASE, NumberOfTransfers, 0, 65535U, 0);


    DMA_enableTrigger(SPIA_HW_TX_DMA_BASE);
    DMA_startChannel(SPIA_HW_TX_DMA_BASE);
    DMA_enableTrigger(SPIA_HW_RX_DMA_BASE);
    DMA_startChannel(SPIA_HW_RX_DMA_BASE);
    EINT;

    DelayUs(10);
}

Uint16 CountDMARxInterrupts = 0;
Uint16 CountDMATxInterrupts = 0;

interrupt void INT_SPIA_HW_RX_DMA_ISR(void)
{
    Uint16 i;

    DMA_stopChannel(SPIA_HW_RX_DMA_BASE);
    DMA_stopChannel(SPIA_HW_TX_DMA_BASE);

    SPI_clearInterruptStatus(SPIA_HW_BASE,SPI_INT_RXFF);
    SPI_clearInterruptStatus(SPIA_HW_BASE,SPI_INT_TXFF);

    DMA_clearTriggerFlag(SPIA_HW_RX_DMA_BASE);
    DMA_clearTriggerFlag(SPIA_HW_TX_DMA_BASE);

    CountDMARxInterrupts++;

    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
}

interrupt void INT_SPIA_HW_TX_DMA_ISR(void)
{

    DMA_stopChannel(SPIA_HW_TX_DMA_BASE);
    SPI_clearInterruptStatus(SPIA_HW_BASE,SPI_INT_TXFF);

    CountDMATxInterrupts++;

    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
}

/**
* Write custom configuration values to the imported modules.
*/
const divider4 = system.clockTree["LOSPCP"];
divider4.divideValue = 6;

const divider5 = system.clockTree["SYSCLKDIVSEL"];
divider5.divideValue = 1;

const multiplier4 = system.clockTree["PLL_IMULT"];
multiplier4.multiplyValue = 10;

const mux8 = system.clockTree["XTAL_OR_X1"];
mux8.inputSelect = "X1";

flash1.$name = "myFMC0";
flash1.enableECC = false;

sci1.useInterrupts = false;
sci1.$name = "mySCIB";
sci1.baudRates = 38400;
sci1.sci.$assign = "SCIB";

spi1.transferProtocol = "SPI_PROT_POL0PHA1";
spi1.$name = "SPIA_HW";
spi1.mode = "SPI_MODE_CONTROLLER";
spi1.bitRate = 6666666;
spi1.dataWidth = "8";
spi1.emulationMode = "SPI_EMULATION_STOP_AFTER_TRANSMIT";
spi1.useDMARX = true;
spi1.useDMATX = true;
spi1.registerInterrupts = true;
spi1.txFifo = "SPI_FIFO_TX8";
spi1.rxFifo = "SPI_FIFO_RX4";
spi1.enabledFIFOInterrupts = ["SPI_INT_RXFF"];
spi1.useInterrupts = false;
spi1.loopback = true;
spi1.spi.$assign = "SPIA";
spi1.spiRXDMA.databusWidthConfig = scripting.forceWrite("DMA_CFG_SIZE_16BIT");
spi1.spiRXDMA.transferSize = 16;
spi1.spiRXDMA.burstSize = 8;
spi1.spiRXDMA.destAddressInputMode = "VARIABLE";
spi1.spiRXDMA.destAddressVariable = "RxSpiDMAData";
spi1.spiRXDMA.useInterrupts = true;
spi1.spiRXDMA.registerInterrupts = true;
spi1.spiRXDMA.enableInterrupts = true;
spi1.spiRXDMA.enableTriggers = true;
spi1.spiRXDMA.interruptMode = "DMA_INT_AT_END";
spi1.spiRXDMA.emulationMode = "DMA_EMULATION_FREE_RUN";
spi1.spiRXDMA.destBurstStep = 1;
spi1.spiRXDMA.destTransferStep = 1;
spi1.spiRXDMA.dmaBase = "DMA_CH2_BASE";
spi1.spiRXDMA.dmaInt.enableInterrupt = true;
spi1.spiTXDMA.databusWidthConfig = scripting.forceWrite("DMA_CFG_SIZE_16BIT");
spi1.spiTXDMA.srcAddressInputMode = "VARIABLE";
spi1.spiTXDMA.srcAddressVariable = "TxSpiDMAData";
spi1.spiTXDMA.burstSize = 8;
spi1.spiTXDMA.transferSize = 16;
spi1.spiTXDMA.useInterrupts = true;
spi1.spiTXDMA.registerInterrupts = true;
spi1.spiTXDMA.enableInterrupts = true;
spi1.spiTXDMA.enableTriggers = true;
spi1.spiTXDMA.interruptMode = "DMA_INT_AT_END";
spi1.spiTXDMA.srcBurstStep = 1;
spi1.spiTXDMA.srcTransferStep = 1;
spi1.spiTXDMA.enablePriority = true;
spi1.spiTXDMA.dmaInt.enableInterrupt = true;

+1 Delaney Woodward over 1 year ago in reply to stevenh

TI__Mastermind 19395 points

Hi Steven,

A couple issues I see with your configurations and code:

Is there a reason you have SPI interrupts enabled? Usually when using SPI and DMA together there should no longer be a need for using SPI interrupts since the DMA should handle all moving of data to free up the CPU.
It looks like you also aren't re-starting the TX DMA channel in the DMA end of transfer interrupt, just stopping it. (Another note: when not in continuous mode, there is no need to call DMA_stopChannel()). This would explain why you are only seeing the transfer happen once. With continuous mode and one-shot mode are disabled, the flow of the DMA module is as follows:
1. Every time the DMA is triggered by the SPI peripheral, it will transfer a burst of data.
2. Once it has transferred the transfer size number of bursts, the DMA channel will be automatically stopped, and the end of transfer DMA interrupt will be called.
3. In order to allow the DMA to transfer more data when the next trigger comes in, you will need to start the channel again in the end of transfer interrupt, as well as clear the DMA interrupt ACK group to receive the next end of transfer DMA interrupt.
Also, your SPI RX FIFO level should be set to 8, the same as your SPI TX FIFO level. You should generally try to match both DMA burst sizes with the FIFO level set. If you have the RX FIFO level set to 4, it will trigger the DMA when there are 4 words present in the RX FIFO, but the DMA will then try to move 8 words to memory. If all 8 words aren't yet present in the RX FIFO, it would move 0's to memory instead of actual data for the last 4 words.

Best Regards,

Delaney

+1 stevenh over 1 year ago in reply to Delaney Woodward

Guru 20045 points

I think I might be closer to solving the issue. There are several non-DMA SPI transmissions that occur before before WiznetReadRegister_DMA() is called. One of the SPI transmissions (highlighted in yellow below) is causing there to be data in the transmit FIFO before WiznetReadRegister_DMA() is called. That transmission is the longer (=21 bytes) than the other non-DMA SPI transmissions (=4 bytes).

Here are the answers to your questions:

Delaney Woodward said:
Is there a reason you have SPI interrupts enabled? Usually when using SPI and DMA together there should no longer be a need for using SPI interrupts since the DMA should handle all moving of data to free up the CPU.

None of the SPI register settings show that SPI interrupts are enabled.

Delaney Woodward said:
It looks like you also aren't re-starting the TX DMA channel in the DMA end of transfer interrupt, just stopping it. (Another note: when not in continuous mode, there is no need to call DMA_stopChannel()). This would explain why you are only seeing the transfer happen once. With continuous mode and one-shot mode are disabled, the flow of the DMA module is as follows:

Yep, that is what I thought but I did it just in case. The WiznetReadRegister_DMA() sets the run bit to start the transfer so Halting the DMA channel at the end of transfer doesn't matter; However, I will remove DMA_stopChannel() from the code.

Delaney Woodward said:
Also, your SPI RX FIFO level should be set to 8, the same as your SPI TX FIFO level. You should generally try to match both DMA burst sizes with the FIFO level set. If you have the RX FIFO level set to 4, it will trigger the DMA when there are 4 words present in the RX FIFO, but the DMA will then try to move 8 words to memory. If all 8 words aren't yet present in the RX FIFO, it would move 0's to memory instead of actual data for the last 4 words.

WiznetReadRegister_DMA() sets both the receive and transmit SPI FIFO level to 8.

+1 stevenh over 1 year ago in reply to Delaney Woodward

Guru 20045 points

Ok, I think I fixed the issue by setting the SPI Rx and TX FIFO level to 16 at the beginning of the SpiTxBytes() function. I also cleared the Rx and Tx FIFO interrupt flag before before exiting that function.

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TMS320F28379D: DMA SPI: Not receiving correct data...Only 1 byte is non-zero