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Original question:

TMS320F28075: Minimum frequency for CPU timer?

TMS320F280049C: Using CPU Timer 2 for 1oo2 Software Voting Using Secondary Free Running Counter

Sorin Cracana
Prodigy 110 points

Part Number: TMS320F280049C

Hello,

We have an application that uses the TI RTOS (without the timestamp module).

We want to use use TIMER2 (with the internal oscilator as a source) as a diagnostic for the TIMER0 (used for the RTOS 1ms tick) 

Timer 0 Uses sys clock (100Mhz) as a source 

Timer 2 Internal Oscillator 1 Clock Source (no prescaler)

Then we configure TIMER 2 to interrupt every millisecond and increase a software counter every time and use that to check against the RTOS ms counter in a 1 second software task.

Observations/question:

1. I noticed that the value calculated with Timer 2 drifts away constantly. 

2. If I was to configure Sysclock as a source for Timer 2 then the counter doesn't drift away but that would no avoid common mode errors

3  In the TRM Chapter 3.7.3.6 it is mentioned that for Timer 2 "If a non-Sysclock source is used, the source must be divided down to no more than half of the sysclck".

Does this mean we cannot use Timer2 for this purpose?

Thank you

  • +1
    TI__Mastermind 30185 points

    Hello Sorin,

    Sorin Cracana said:
    1. I noticed that the value calculated with Timer 2 drifts away constantly. 

    Can you provide details on this constant drift value? Is it accountable within the datasheet specifications for the INTOSC?

    If so, then this drift might be expected. If not, you might also want to check any other sources of delay such as contents within the ISR itself.

    Sorin Cracana said:

    3  In the TRM Chapter 3.7.3.6 it is mentioned that for Timer 2 "If a non-Sysclock source is used, the source must be divided down to no more than half of the sysclck".

    Does this mean we cannot use Timer2 for this purpose?

    This TRM detail essentially means INTOSC (non-SYSCLK source) <= SYSCLK/2. In other words, the prescaler value must be set so INTOSC is not greater than half of SYSCLK. If SYSCLK is 100MHz, then the non-SYSCLK source must be 50MHz or lower, so I don't think this would cause a problem for your situation.

  • 0
    Prodigy 110 points

    Sorry for late reply.

    It turned out i had a bug in the calculation code.

    The drift is iwthin the data specs. Thanks again