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TMS320F280041-Q1: Why 60 cycle delay needed when configuring/initializing PLL?

Part Number: TMS320F280041-Q1

Hi BU experts, 

I am asking this issue for my customer. 

In their application, they configured IMUL-10, FMUL-0, DIV-2 in bootloader and configured IMUL-5, FMUL-0, DIV-1 in application. And they found that the system will be reset by NMIWD. After debugging, found that it is caused by Flash ECC error and this error is happened when executes ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; and ClkCfgRegs.SYSPLLMULT.all = temp_syspllmult; in PLL initializing codes. Since they are using old version driver for F28004x. And they don't have insert the following 60 cycle delay between the above 2 codes. 

After adding the delay, the system can work fine. But customer need TI to answer the following questions

1) why this delay is needed? And when not add this delay, why the Flash will report ECC error? What is the hardware mechanism behind this? 

2) in the early design, the BootLoader and APP are both configuring IMUL-10, FMUL-0, DIV-2, and they forced the APP to execute ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; and ClkCfgRegs.SYSPLLMULT.all = temp_syspllmult. But there is no error nor reset happened in this condition. Need an explanation. 

Regards, 

Will

  • Hi BU team, 

    Any comments? 

  • Hello Will,

    Apologies for the delayed response here. This is a hardware requirement that is documented in the device TRM (see note in section 3.7.11 (System Control and Interrupts > Clocking > Clock Configuration Examples) and is required for glitch-free transition from one clock source to another. If this 60-cycle delay is skipped, device instability could occur. A 60-cycle delay must be implemented whenever the PLL is bypassed or the OSCCLK source is switched.

    Best regards,
    Ibukun