Original question:
hello:
i have a question that disturb me long time.
master request 3C,when 3D response ,disturbe the frame in byte1 stop bit ,it trigger a bit error, it should show in response error bit
but in fact,after service the BE error interrupt the busy bit in SCIFLR is set always, it lead the frist frame abnormal and second frame is ok 
how to clear the busy bit in SCIFLR ?
how to clear the transmit buffer or receive buffer?
Hello,
In order to clear the BUSY bit in the SCIFLR register, you have to do one of the following:
Are you saying that after reception of the next sync break the BE flag is still set?
Since data isn't actually transmitted until the message ID is written, the transmit buffer can be cleared/overwritten any time before that by simply clearing the LINTD0 and LINTD1 registers. Once the LINID has been set, the LIN module will immediately begin transmitting data from each field of the TD buffer. For the RX buffer, the LINRD0 and LINRD1 registers are read only. So, there should be no way to clear its values. However, the best approach would be to read the data and discard if needed. Let me know if that answers your question.
Best Regards,
Delaney
