TMS320F28020: GPIO CMOS slow input

Genius 3186 points

Part Number: TMS320F28020

May I have question about F28020 GPIO input?

The customer's system has a slow GPIO input signal rise time, which can cause CMOS inrush current problems.

I find document about CMOS slow input signal.

https://www.ti.com/lit/an/scba004e/scba004e.pdf?ts=1685333735887

Can this document be applied to F 28020?

And Which type is CMOS in F28020?

Thanks,

over 2 years ago

0 Omer Amir over 2 years ago

TI__Mastermind 30185 points

Hello,

GR said:
The customer's system has a slow GPIO input signal rise time, which can cause CMOS inrush current problems.

What sort of rise time is the customer seeing? Is it within the datasheet specifications?

0 GR over 2 years ago in reply to Omer Amir

Genius 3186 points

Hello Amir,

Thanks for your supporting.

Omer Amir said:
What sort of rise time is the customer seeing? Is it within the datasheet specifications?

The rise/fall time of the GPIO input is not shown in the data sheet,

The rise time is considered to be slow enough that the through-current of CMOS is generally a problem.

GR said:
And Which type is CMOS in F28020?

And Is there any information about this?

Best regards,

0 Omer Amir over 2 years ago in reply to GR

TI__Mastermind 30185 points

Hello,

GR said:
And Is there any information about this?

I don't believe we are allowed to disclose such design details, but I will ask our design team if the application report you mentioned applies to the GPIO on our devices.

0 GR over 2 years ago in reply to Omer Amir

Genius 3186 points

Hello Amir,

Thank you.

I will be waiting for the design team to respond.

Best regards,

+1 Omer Amir over 2 years ago in reply to GR

TI__Mastermind 30185 points

Hello,

I talked with the design team and this was the information they provided:

The GPIO input is a CMOS receiver, please check that if the input slew rate is less than 30%/frequency of operation. The concern here is violation of EM limits; peak current should not increase with larger rise/fall times. For average and RMS currents, if the frequency also scales (reduces) with higher rise/fall times then the usage should be within in the EM limits.

0 GR over 2 years ago in reply to Omer Amir

Genius 3186 points

Hello,

Thanks for your supporting.

I understand about nrush current.

And How was through-current of CMOS?

GR said:
The rise time is considered to be slow enough that the through-current of CMOS is generally a problem.

What is the voltage rise time below when the CMOS turns on simultaneously and the through-current becomes a problem?

Best regards,

0 Omer Amir over 2 years ago in reply to GR

TI__Mastermind 30185 points

Hello,

I will reach out to the design experts and try to get a response by the end of the week if possible.

+1 Luke Jones over 2 years ago in reply to Omer Amir

TI__Mastermind 28580 points

Hi GR,

The design team responded back. They reiterated that the through current will only become a problem when the voltage rise time is greater than 30% of the switching period. There is no fixed maximum rise time as this depends on the switching frequency of the GPIO input.

Thank you,

Luke

0 GR over 2 years ago in reply to Luke Jones

Genius 3186 points

Hi Luke,

Thanks for your supporting.

I understand maximum rising time is 30％ of switching period.

I want to know minimum rising time as ~ns/V.

Or you mean there is a different t hreshold in the turn on/off time of the CMOS hi-side FET and the low-side FET.
Are you saying that the input of 1 s/V is acceptable?

Best regards,

0 Luke Jones over 2 years ago in reply to GR

TI__Mastermind 28580 points

Hi GR,

I am awaiting a response from the design team on this question. I will get back to you as soon as I have more information.

Thank you,

Luke

0 Luke Jones over 2 years ago in reply to Luke Jones

TI__Mastermind 28580 points

Hi GR,

To my knowledge there is no minimum rise time but I am still waiting on confirmation from the design team. Let me know if you still need confirmation on this.

Thank you,

Luke

+1 Luke Jones over 2 years ago in reply to Luke Jones

TI__Mastermind 28580 points

Hi GR,

The design team responded back, there is no minimum rise time requirement.

Thank you,

Luke

0 GR over 2 years ago in reply to Luke Jones

Genius 3186 points

Hi Luke,

Thanks for your information and checking to design team.

I understand it.

Thank you very much.

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TMS320F28020: GPIO CMOS slow input