ADC Clock

Hallo !

Regarding PICCOLO TMS320F28069,

Someone could help me to fill this table out

ADCCTL2 Register at  SYSCLKOUT = 80Mhz  

CLKDIV4EN         CLKDIV2EN         ADC Clock

         0                            0                              ?
         0                            1                              ?
         1                            0                              ?
         1                            1                              ?

Another point is related to "tms320f28069.pdf" and "spruh18b.pdf"

The first document limit the maximun frequency of ADCCLK at 40 MHz and

The second document give us the Table 8.1 wich refers to ADCCLK at 60 MHz
( Ok, it is a preliminary document ! )

It seems a little bit confuse for me !!!!

Thanks a lot for your attention

Wail