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Hi.
Our microcontroller is communicating through RS485 (THVD2450 + TS3USB221E) protocol using SCI peripheral.
We are facing a problem as the master and our board have swapped signals (RS485+/-).
As we don't want the user to modify the interconnect cable we plan to do that by software.
On the "Technical Reference Manual" I see that there is a register to invert Rx pin but I don't see the same on output. Can you confirm me this?
Otherwise is there this kind of function on SCI Tx?
Sincerely.
Jérôme
Hi Jerome,
Where do you see this register?
There is an output override function on the CLB that can override the SCI RX line. You may be able to take the GPIO used for SCI RX as an input to the CLB, invert it within the CLB, and then enable the output override function for SCI RX to effectively invert the signal coming into SCI.
Thank you,
Luke
Hi Luke
I think that using GPyINV register is enough to invert the SCI input and I was able to do so.
My question is on the SCI Tx side. Is it possible to invert the output in the SCI peripheral or on the GPIO?
Sincerely.
Jérôme
Hey Jerome,
You can use a similar approach for SCI_TX using the CLB. SCI_TX can be used as a input to the CLB which can then be inverted. Which GPIO are you using for SCITX? It may not be possible to do this depending on the mux options for that GPIO.
Thank you,
Luke
Hi Luke.
Thank you for your reply. That's a great idea. Indeed SCI_C Tx is available on the local CLB7 input.
But as I am using GPIO12 (C2 pin), output X-BAR is not available on this pin.
Thanks anyway.
Jérôme
Hey Jerome,
There may still be another way...
Are you using EPWM7A? You can use the CLB output override function to replace EPWM7A with your inverted SCITX signal and route it to GPIO12.
Thank you,
Luke
Hi Luke
No I'm not using the EPWM7A. You are right it is available on CLB7 output and on GPIO12 (C2) too.
I will try in the next days and I will tell you.
Thank you for your help.
Jérôme
Sounds good, let me know if you need assistance implementing this. I recommend using SysConfig for the CLB configuration.