Hi all!
I'm trying to configure the TZ5 and I don't know if I do it wrong or test it wrong.
Here is what I'm doing:
// Set CLOCKFAIL
SysCtrlRegs.CLKCTL.bit.NMIRESETSEL = 1; // enable the generation of the CLOCKFAIL signal
NmiIntruptRegs.NMICFG.bit.CLOCKFAIL = 1; // CLOCKFAIL Interrupt Enabled
NmiIntruptRegs.NMIWDPRD = 0xFFFF; // default
// Enable Trip Zone
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // 3=TZ5
// Enable TZ5 as one cycle-by-cycle trip sources
EALLOW;
EPwm2Regs.TZSEL.bit.CBC5 = 1;
// What do we want the TZ5 and TZ6 to do?
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
// Enable TZ interrupt
EPwm2Regs.TZEINT.bit.CBC = 1;
EDIS;
interrupt void nmi_isr(void)
{
NMIIntCount++;
// Clear the flags
EALLOW;
NmiIntruptRegs.NMIFLGCLR.bit.CLOCKFAIL = 1;
NmiIntruptRegs.NMIFLGCLR.bit.NMIINT = 1;
EDIS;
}
Somewhere in the code I force a clockfail:
EALLOW;
NmiIntruptRegs.NMIFLGFRC.bit.CLOCKFAIL = 1;
EDIS;
I can see NMIIntCount was incremented, so the execution gets in the isr, but the PWM are not in low.I don't understand exactly how this should work, I thought TZ5 will first put the PWM in low and after that NMI_ISR will be executed.
Can somebody clarify this?
Thanks a lot,
Monica