LAUNCHXL-F28379D: CMD_init() error

Hi Juan,

Can you show any dissembly, process in how you setup the sysconfig tool for computing FFT? I assume you're running from RAM right now correct? Are you using the sysconfig tool for linker command support?

Can you show me what is contained in your CMD init function?

Best,

Ryan Ma

Hi Ryan,

Thank you for your prompt response. I'm currently configuring the sysconfig tool for computing the FFT, and here's the setup:

However, I seem to be encountering an issue even before reaching the FFT computation stage. The code I'm working with is as follows:

//
// Included Files
//
#include "driverlib.h"
#include "device.h"
#include "board.h"
#include "c2000ware_libraries.h"

#define INPUT_SIZE 1537

//
// Globals
//

float32_t *inpPtr, *outPtr, *magPtr, *phaPtr, *twiPtr;

float32_t inpBuff[myRFFT0_RFFT_SIZE], outBuff[myRFFT0_RFFT_SIZE], twiBuff[myRFFT0_RFFT_SIZE], magBuff[myRFFT0_RFFT_SIZE / 2 + 1], phaBuff[myRFFT0_RFFT_SIZE / 2];

float32_t I3aRe[INPUT_SIZE], I3aIm[INPUT_SIZE], I3aMag[INPUT_SIZE], I3aPha[INPUT_SIZE];

int16_t testidx;

//
// Main
//
void main(void)
{
    //
    // Locals
    //

    int16_t i, idxJan;

    float32_t i3a[INPUT_SIZE] = {
        #include "i3a.h"
    };
    idxJan = 0;
    testidx = 0;

    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Disable pin locks and enable internal pull-ups.
    //
    Device_initGPIO();

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // PinMux and Peripheral Initialization
    //
    Board_init();

    //
    // C2000Ware Library initialization
    //
    C2000Ware_libraries_init();

    //
    // Enable Global Interrupt (INTM) and real time interrupt (DBGM)
    //
    EINT;
    ERTM;

    while(1)
    {
        
    }
}

//
// End of File
//

I've started from scratch to rule out any errors on my part, but it seems that even this simple setup is resulting in an error. This is my first time using the sysconfig tool, and unfortunately, the experience hasn't been very smooth so far.

I'm running the code from RAM and leveraging the sysconfig tool for linker command support.

Here's the CDM_init function:

void CMD_init()
{
#ifdef MEM_CONF
      MEM_CONF_init();
#endif

}

I'd appreciate any insights you might have on what could be causing the issue.

Hi Juan,

I apologize for any inconveniences, and will work on providing a solution for you.

If you go to MEM_CONF_init(), What's in the MEM_CONF_init() function? 

Best,

Ryan Ma

Hia Ryan,

Thank you for the response.

The function is the following:

#ifdef MEM_CONF
void MEM_CONF_init()
{
}
#endif

There is a MEM_CONF_init with the following content:

//*****************************************************************************
//
// MEMCFG Configurations
//
//*****************************************************************************
void MEMCFG_init(){
	//
	// Initialize RAMs
	//
	//
	// Configure LSRAMs
	//
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS0, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS1, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS2, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS3, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS4, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS5, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	//
	// Configure GSRAMs
	//
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS0, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS1, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS2, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS3, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS4, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS5, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS6, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS7, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS8, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS9, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS10, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS11, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS12, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS13, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS14, MEMCFG_GSRAMCONTROLLER_CPU1);
	MemCfg_setGSRAMControllerSel(MEMCFG_SECT_GS15, MEMCFG_GSRAMCONTROLLER_CPU1);
	//
	// ROM Access Configuration
	//
	MemCfg_enableROMWaitState();
	MemCfg_disableROMPrefetch();
	//
	// Configure Access Protection for RAMs
	//
	MemCfg_setProtection(MEMCFG_SECT_D0, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_D1, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS0, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS1, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS2, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS3, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS4, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS5, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS0, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS1, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS2, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS3, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS4, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS5, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS6, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS7, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS8, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS9, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS10, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS11, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS12, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS13, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS14, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS15, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	//
	// Lock/Commit Registers
	//
	//
	// Enable Access Violation Interrupt
	//
	//
	// Correctable error Interrupt
	//
	MemCfg_setCorrErrorThreshold(0);
	MemCfg_disableCorrErrorInterrupt(MEMCFG_CERR_CPUREAD);
} 

Hi Juan,

did you create your own CMD_init() function or are you using the generated one from syscfg? can you share a screenshot of your syscfg and the generated files? Are they all included in the build?

Are you using sysconfig to help with memory configuration? 

Best,

Ryan Ma

Dear Ryan,

I am using the functions generated by the sysconfig tool. The generated files are the following:

The build is completed without errors or warnings.

Best regards,

Juan Ramón Camarillo

Hi Juan,

Apologize for the delay, is the program failing at MEM_CONF_init or MEMCFG_init?

If CMD_init() is an empty function it should not fail at this point and return from this.

Best,

Ryan Ma

Hi Ryan,

To be honest, I don't know where the program is failing. I made some alterations compared to the last conversation, but the program always crashes. The new fail point is the following:

Hi Juan,

Thank you for providing the screenshot of where it is failing. Are you using the correct clock source in the clock tree tool? 

Are you using the latest C2000WARE? Can you provide your syscfg source code? 

Best,

Ryan Ma

Hi Ryan,

I don't know if I am using the correct clock source. Yes, I am using the latest C2000WARE (5.02.00.00).

The sysconfig source code is the following:

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "F2837xD" --package "F2837xD_100PTP" --part "F2837xD_100PTP" --context "CPU1" --product "C2000WARE@5.02.00.00"
 * @versions {"tool":"1.20.0+3587"}
 */

/**
 * Import the modules used in this configuration.
 */
const memcfg = scripting.addModule("/driverlib/memcfg.js");
const sysctl = scripting.addModule("/driverlib/sysctl.js");
const FFT    = scripting.addModule("/libraries/dsp/FPU/FFT/FFT.js", {}, false);
const FFT1   = FFT.addInstance();
const CMD    = scripting.addModule("/utilities/cmd_tool/cmd_syscfg/source/CMD", {}, false);
const CMD1   = CMD.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
FFT1.$name                  = "myFFT0";
FFT1.RFFT.create(1);
FFT1.RFFT[0].$name          = "myRFFT0";
FFT1.RFFT[0].sincosFunction = false;
FFT1.RFFT[0].inPtr          = "inpPtr";
FFT1.RFFT[0].outPtr         = "outPtr";
FFT1.RFFT[0].magPtr         = "magPtr";
FFT1.RFFT[0].phasPtr        = "phaPtr";
FFT1.RFFT[0].coeffPtr       = "twiPtr";

CMD1.$name                                 = "MEM_CONF";
CMD1.sectionMemory_text                    = ["RAMD_COMB","RAMLS_COMB"];
CMD1.sectionMemory_ramfunc                 = ["RAMM_COMB"];
CMD1.sectionMemory_cinit                   = ["RAMM_COMB"];
CMD1.sectionMemory_stack                   = ["RAMM_COMB"];
CMD1.sectionMemory_init_array              = ["RAMM_COMB"];
CMD1.sectionMemory_bss                     = ["RAMLS_COMB"];
CMD1.sectionMemory_const                   = ["RAMLS_COMB"];
CMD1.sectionMemory_data                    = ["RAMLS_COMB"];
CMD1.sectionMemory_switch                  = ["RAMM_COMB"];
CMD1.sectionMemory_sysmem                  = ["RAMLS_COMB"];
CMD1.RAMMmemoryCombination.create(1);
CMD1.RAMMmemoryCombination[0].$name        = "RAMM_COMB";
CMD1.RAMMmemoryCombination[0].combination  = ["RAMM0","RAMM1"];
CMD1.RAMDmemoryCombination.create(1);
CMD1.RAMDmemoryCombination[0].$name        = "RAMD_COMB";
CMD1.RAMDmemoryCombination[0].combination  = ["RAMD0","RAMD1"];
CMD1.RAMLSmemoryCombination.create(1);
CMD1.RAMLSmemoryCombination[0].$name       = "RAMLS_COMB";
CMD1.RAMLSmemoryCombination[0].combination = ["RAMLS0","RAMLS1","RAMLS2","RAMLS3","RAMLS4","RAMLS5"];
CMD1.RAMGSmemoryCombination.create(1);
CMD1.RAMGSmemoryCombination[0].$name       = "RAMGS_COMB";
CMD1.RAMGSmemoryCombination[0].combination = ["RAMGS0","RAMGS1","RAMGS10","RAMGS11","RAMGS12","RAMGS13","RAMGS14","RAMGS15","RAMGS2","RAMGS3","RAMGS4","RAMGS5","RAMGS6","RAMGS7","RAMGS8","RAMGS9"];
CMD1.FLASHmemoryCombination.create(1);
CMD1.FLASHmemoryCombination[0].$name       = "FLASH_COMB";
CMD1.FLASHmemoryCombination[0].combination = ["FLASHA","FLASHB","FLASHC","FLASHD","FLASHE","FLASHF","FLASHG","FLASHH","FLASHI","FLASHJ","FLASHK","FLASHL","FLASHM","FLASHN"];

Best regards,

Juan Ramón Camarillo

Hi Juan,

The error you posted seems to be due to the defines related to clock configuration settings in device.h.

Can you screenshot what build configuration you're using with your CCS project? Go to project properties -> build configurations -> set active -> select CPU1_LAUNCHXL_RAM. Since you're using a launchpad I assume, make sure you select the LAUNCXL build configuration.

Hi Ryan,

I don't have that option. This is the screenshot of my build configuration options:

This may be why you're running into a clock configuration issue.

Can you show me your device.h file? Can you check to see if the launchpad configurations are being used?

Hi Ryan,

As you pointed out, the launchpad configurations are not being used. This is my device.h file:

//#############################################################################
//
// FILE:   device.h
//
// TITLE:  Device setup for examples.
//
//#############################################################################
//
// $Release Date: $
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################

//
// Included Files
//
#include "driverlib.h"

#if (!defined(CPU1) && !defined(CPU2))
#error "You must define CPU1 or CPU2 in your project properties.  Otherwise, \
the offsets in your header files will be inaccurate."
#endif

#if (defined(CPU1) && defined(CPU2))
#error "You have defined both CPU1 and CPU2 in your project properties.  Only \
a single CPU should be defined."
#endif

//*****************************************************************************
//
// Defines for pin numbers and other GPIO configuration
//
//*****************************************************************************
//
// LEDs
//
#ifdef _LAUNCHXL_F28379D
#define DEVICE_GPIO_PIN_LED1        31U  // GPIO number for LD10
#define DEVICE_GPIO_PIN_LED2        34U  // GPIO number for LD9
#define DEVICE_GPIO_CFG_LED1        GPIO_31_GPIO31  // "pinConfig" for LD10
#define DEVICE_GPIO_CFG_LED2        GPIO_34_GPIO34  // "pinConfig" for LD9
#else
#define DEVICE_GPIO_PIN_LED1        31U  // GPIO number for LD2
#define DEVICE_GPIO_PIN_LED2        34U  // GPIO number for LD3
#define DEVICE_GPIO_CFG_LED1        GPIO_31_GPIO31  // "pinConfig" for LD2
#define DEVICE_GPIO_CFG_LED2        GPIO_34_GPIO34  // "pinConfig" for LD3
#endif


//
// SCI for USB-to-UART adapter on FTDI chip
//
#ifdef _LAUNCHXL_F28379D
#define DEVICE_GPIO_PIN_SCIRXDA     43U             // GPIO number for SCI RX
#define DEVICE_GPIO_PIN_SCITXDA     42U             // GPIO number for SCI TX
#define DEVICE_GPIO_CFG_SCIRXDA     GPIO_43_SCIRXDA // "pinConfig" for SCI RX
#define DEVICE_GPIO_CFG_SCITXDA     GPIO_42_SCITXDA // "pinConfig" for SCI TX
#else
#define DEVICE_GPIO_PIN_SCIRXDA     28U             // GPIO number for SCI RX
#define DEVICE_GPIO_PIN_SCITXDA     29U             // GPIO number for SCI TX
#define DEVICE_GPIO_CFG_SCIRXDA     GPIO_28_SCIRXDA // "pinConfig" for SCI RX
#define DEVICE_GPIO_CFG_SCITXDA     GPIO_29_SCITXDA // "pinConfig" for SCI TX
#endif

//
// GPIO assignment for CAN-A and CAN-B
//
#ifdef _LAUNCHXL_F28379D
#define DEVICE_GPIO_CFG_CANRXA      GPIO_36_CANRXA  // "pinConfig" for CANA RX
#define DEVICE_GPIO_CFG_CANTXA      GPIO_37_CANTXA  // "pinConfig" for CANA TX
#define DEVICE_GPIO_CFG_CANRXB      GPIO_17_CANRXB  // "pinConfig" for CANB RX
#define DEVICE_GPIO_CFG_CANTXB      GPIO_12_CANTXB  // "pinConfig" for CANB TX
#else
#define DEVICE_GPIO_CFG_CANRXA      GPIO_30_CANRXA  // "pinConfig" for CANA RX
#define DEVICE_GPIO_CFG_CANTXA      GPIO_31_CANTXA  // "pinConfig" for CANA TX
#define DEVICE_GPIO_CFG_CANRXB      GPIO_10_CANRXB  // "pinConfig" for CANB RX
#define DEVICE_GPIO_CFG_CANTXB      GPIO_8_CANTXB   // "pinConfig" for CANB TX

//I2CA GPIO pins
#define DEVICE_GPIO_PIN_SDAA    104
#define DEVICE_GPIO_PIN_SCLA    105

#define DEVICE_GPIO_CFG_SDAA GPIO_104_SDAA
#define DEVICE_GPIO_CFG_SCLA GPIO_105_SCLA


//I2CB GPIO pins
#define DEVICE_GPIO_PIN_SDAB    40
#define DEVICE_GPIO_PIN_SCLB    41

#define DEVICE_GPIO_CFG_SDAB GPIO_40_SDAB
#define DEVICE_GPIO_CFG_SCLB GPIO_41_SCLB

#endif

//*****************************************************************************
//
// Defines related to clock configuration
//
//*****************************************************************************
//
// Launchpad Configuration
//
#ifdef _LAUNCHXL_F28379D

//
// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock().
//
#define DEVICE_OSCSRC_FREQ          10000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
//
#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) |  \
                                     SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |   \
                                     SYSCTL_PLL_ENABLE)

//
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2)

//
// ControlCARD Configuration
//
#else

//
// 20MHz XTAL on controlCARD. For use with SysCtl_getClock().
//
#define DEVICE_OSCSRC_FREQ          20000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
//
#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) |  \
                                     SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |   \
                                     SYSCTL_PLL_ENABLE)

//
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2)

#endif

//
// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
// low speed peripheral clock divider of 4. Update the code below if a
// different LSPCLK divider is used!
//
#define DEVICE_LSPCLK_FREQ          (DEVICE_SYSCLK_FREQ / 4)

//*****************************************************************************
//
// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
// will convert the desired delay in microseconds to the count value expected
// by the function. \b x is the number of microseconds to delay.
//
//*****************************************************************************
#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L /  \
                              (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L)

//
// The macros that can be used as parameter to the function Device_bootCPU2
//
#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL                        0x00000000U
#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI                             0x00000001U
#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI                             0x00000004U
#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C                             0x00000005U
#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN                             0x00000007U
#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM                             0x0000000AU
#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH                           0x0000000BU

//
// Other macros that are needed for the Device_bootCPU2 function
//
#define BROM_IPC_EXECUTE_BOOTMODE_CMD                                0x00000013U
#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE            0x0000000CU
#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE                             0x00000000U
#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT                         0x00000001U
#define C2_BOOTROM_BOOTSTS_SYSTEM_READY                              0x00000002U
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK                       0x00000003U
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED  0x00000004U
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005U

//
// Macros used as return value by the Device_bootCPU2 function
//
#define STATUS_FAIL                 0x0001
#define STATUS_PASS                 0x0000

//*****************************************************************************
//
// Defines, Globals, and Header Includes related to Flash Support
//
//*****************************************************************************
#ifdef _FLASH
#include <stddef.h>

extern uint16_t RamfuncsLoadStart;
extern uint16_t RamfuncsLoadEnd;
extern uint16_t RamfuncsLoadSize;
extern uint16_t RamfuncsRunStart;
extern uint16_t RamfuncsRunEnd;
extern uint16_t RamfuncsRunSize;

#define DEVICE_FLASH_WAITSTATES 3

#endif

extern uint32_t Example_PassCount;
extern uint32_t Example_Fail;

//*****************************************************************************
//
// Function Prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup device_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
//! @brief Function to initialize the device. Primarily initializes system control to a
//! known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
//! and enabling the clocks to the peripherals.
//!
//! \param None.
//! \return None.
//
//*****************************************************************************
extern void Device_init(void);
//*****************************************************************************
//!
//!
//! @brief Function to turn on all peripherals, enabling reads and writes to the
//! peripherals' registers.
//!
//! Note that to reduce power, unused peripherals should be disabled.
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_enableAllPeripherals(void);
//*****************************************************************************
//!
//!
//! @brief Function to disable pin locks on GPIOs.
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_initGPIO(void);
//*****************************************************************************
//!
//! @brief Function to enable pullups for the unbonded GPIOs on the 176PTP package:
//! GPIOs     Grp Bits
//! 95-132    C   31
//!           D   31:0
//!           E   4:0
//! 134-168   E   31:6
//!           F   8:0
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_enableUnbondedGPIOPullupsFor176Pin(void);
//*****************************************************************************
//!
//! @brief Function to enable pullups for the unbonded GPIOs on the 100PZ package:
//! GPIOs     Grp Bits
//! 0-1       A   1:0
//! 5-9       A   9:5
//! 22-40     A   31:22
//!           B   8:0
//! 44-57     B   25:12
//! 67-68     C   4:3
//! 74-77     C   13:10
//! 79-83     C   19:15
//! 93-168    C   31:29
//!           D   31:0
//!           E   31:0
//!           F   8:0
//! @param None
//! @return None
//
//
//*****************************************************************************
extern void Device_enableUnbondedGPIOPullupsFor100Pin(void);
//*****************************************************************************
//!
//! @brief Function to enable pullups for the unbonded GPIOs on the
//! 176PTP package.
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_enableUnbondedGPIOPullups(void);
#ifdef CPU1
//*****************************************************************************
//!
//! @brief Function to implement Analog trim of TMX devices
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_configureTMXAnalogTrim(void);
//*****************************************************************************
//! @brief Executes a CPU02 control system bootloader.
//!
//! \param bootMode specifies which CPU02 control system boot mode to execute.
//!
//! This function will allow the CPU01 master system to boot the CPU02 control
//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
//! SCI, I2C, or parallel I/O. This function blocks and waits until the
//! control system boot ROM is configured and ready to receive CPU01 to CPU02
//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and
//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the
//! command to execute the selected bootloader.
//!
//! The \e bootMode parameter accepts one of the following values:
//!  - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL
//!  - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI
//!  - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI
//!  - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C
//!  - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN
//!  - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM
//!  - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH
//!
//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
//! invalid and command was not sent.
//
//*****************************************************************************
extern uint16_t Device_bootCPU2(uint32_t ulBootMode);
#endif
//*****************************************************************************
//!
//! @brief Error handling function to be called when an ASSERT is violated
//!
//! @param *filename File name in which the error has occurred
//! @param line Line number within the file
//! @return None
//
//*****************************************************************************
extern void __error__(const char *filename, uint32_t line);
extern void Example_setResultPass(void);
extern void Example_setResultFail(void);
extern void Example_done(void);

//
// End of file
//

Hi Ryan,

I put the _LAUNCXL_F28379D in the build configuration and end up with the same error.

I tried on two different computers just to be sure.

Hi Ryan,

I wanted to inform you that I've recently enabled the "Active a Linker CMD Configuration" feature in addition to defining the _LAUNCXL_F28379D. Fortunately, I'm no longer encountering the previous error message. However, I now see a new message: "Break at address '0x820f8' with no debug information available, or outside of program code." As far as I understand, this message doesn't indicate an error, but I'm uncertain how to prevent it from occurring.

Best regards,

Juan Ramón Camarillo

Hi Juan,

Okay great, can you confirm that you're able to reach the infinite while loop now? Can you run to the while(1) line before this new issue you're describing occurs?

Where is it breaking before you receive the error message? 

Best,

Ryan Ma

Hi Ryan,

It breaks at the very Device_init() function. It just initializes the local variables.

Best,

Juan Ramón Camarillo

Hi Juan,

Can you please share the error from compiler that is happening? What function within Device_init() is failing? Can you step into the function and do a step over to see what may be failing?

Can you share your latest .syscfg file and main.c file?

Best,

Ryan Ma

Hi Ryan,

The message that I am having is "Break at address "0x820f0" with no debug information available, or outside of program code.".

The function that is failling is the CMD_init(). The last line reached is the following:

My lastest sysconfig file is the following:

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "F2837xD" --package "F2837xD_100PTP" --part "F2837xD_100PTP" --context "CPU1" --product "C2000WARE@5.02.00.00"
 * @versions {"tool":"1.20.0+3587"}
 */

/**
 * Import the modules used in this configuration.
 */
const memcfg = scripting.addModule("/driverlib/memcfg.js");
const sysctl = scripting.addModule("/driverlib/sysctl.js");
const FFT    = scripting.addModule("/libraries/dsp/FPU/FFT/FFT.js", {}, false);
const FFT1   = FFT.addInstance();
const CMD    = scripting.addModule("/utilities/cmd_tool/cmd_syscfg/source/CMD");
const CMD1   = CMD.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
FFT1.$name                  = "myFFT0";
FFT1.RFFT.create(1);
FFT1.RFFT[0].$name          = "myRFFT0";
FFT1.RFFT[0].sincosFunction = false;
FFT1.RFFT[0].inPtr          = "inpPtr";
FFT1.RFFT[0].outPtr         = "outPtr";
FFT1.RFFT[0].magPtr         = "magPtr";
FFT1.RFFT[0].phasPtr        = "phaPtr";
FFT1.RFFT[0].coeffPtr       = "twiPtr";

CMD.activateCMD = true;
CMD.activeCMD   = "MEM_CONF";

CMD1.$name                                 = "MEM_CONF";
CMD1.sectionMemory_text                    = ["RAMD_COMB","RAMLS_COMB"];
CMD1.sectionMemory_ramfunc                 = ["RAMM_COMB"];
CMD1.sectionMemory_cinit                   = ["RAMM_COMB"];
CMD1.sectionMemory_stack                   = ["RAMM_COMB"];
CMD1.sectionMemory_init_array              = ["RAMM_COMB"];
CMD1.sectionMemory_bss                     = ["RAMLS_COMB"];
CMD1.sectionMemory_const                   = ["RAMLS_COMB"];
CMD1.sectionMemory_data                    = ["RAMLS_COMB"];
CMD1.sectionMemory_switch                  = ["RAMM_COMB"];
CMD1.sectionMemory_sysmem                  = ["RAMLS_COMB"];
CMD1.RAMMmemoryCombination.create(1);
CMD1.RAMMmemoryCombination[0].$name        = "RAMM_COMB";
CMD1.RAMMmemoryCombination[0].combination  = ["RAMM0","RAMM1"];
CMD1.RAMDmemoryCombination.create(1);
CMD1.RAMDmemoryCombination[0].$name        = "RAMD_COMB";
CMD1.RAMDmemoryCombination[0].combination  = ["RAMD0","RAMD1"];
CMD1.RAMLSmemoryCombination.create(1);
CMD1.RAMLSmemoryCombination[0].$name       = "RAMLS_COMB";
CMD1.RAMLSmemoryCombination[0].combination = ["RAMLS0","RAMLS1","RAMLS2","RAMLS3","RAMLS4","RAMLS5"];
CMD1.RAMGSmemoryCombination.create(1);
CMD1.RAMGSmemoryCombination[0].$name       = "RAMGS_COMB";
CMD1.RAMGSmemoryCombination[0].combination = ["RAMGS0","RAMGS1","RAMGS10","RAMGS11","RAMGS12","RAMGS13","RAMGS14","RAMGS15","RAMGS2","RAMGS3","RAMGS4","RAMGS5","RAMGS6","RAMGS7","RAMGS8","RAMGS9"];
CMD1.FLASHmemoryCombination.create(1);
CMD1.FLASHmemoryCombination[0].$name       = "FLASH_COMB";
CMD1.FLASHmemoryCombination[0].combination = ["FLASHA","FLASHB","FLASHC","FLASHD","FLASHE","FLASHF","FLASHG","FLASHH","FLASHI","FLASHJ","FLASHK","FLASHL","FLASHM","FLASHN"];

My lastest main function is the following:

//
// Included Files
//
#include "driverlib.h"
#include "device.h"
#include "board.h"
#include "c2000ware_libraries.h"

#define INPUT_SIZE 1537
#define _LAUNCHXL_F28379D

//
// Globals
//

float32_t *inpPtr, *outPtr, *magPtr, *phaPtr, *twiPtr;

float32_t inpBuff[myRFFT0_RFFT_SIZE], outBuff[myRFFT0_RFFT_SIZE], twiBuff[myRFFT0_RFFT_SIZE], magBuff[myRFFT0_RFFT_SIZE / 2 + 1], phaBuff[myRFFT0_RFFT_SIZE / 2];

float32_t I3aRe[INPUT_SIZE], I3aIm[INPUT_SIZE], I3aMag[INPUT_SIZE], I3aPha[INPUT_SIZE];

int16_t testidx;

//
// Main
//
void main(void)
{
    //
    // Locals
    //

    int16_t i, idxJan;

    float32_t i3a[INPUT_SIZE] = {
        #include "i3a.h"
    };
    idxJan = 0;
    testidx = 0;

    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Disable pin locks and enable internal pull-ups.
    //
    Device_initGPIO();

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // PinMux and Peripheral Initialization
    //
    Board_init();

    //
    // C2000Ware Library initialization
    //
    C2000Ware_libraries_init();

    //
    // Enable Global Interrupt (INTM) and real time interrupt (DBGM)
    //
    EINT;
    ERTM;

    while(1)
    {
        
    }
}

//
// End of File
//

Best,

Juan Ramón Camarillo

Hi Juan,

I see this may be a linker command configuration issue. Let me loop in the correct expert that can further debug this issue. Can you give some more details as to why you're combining memory regions?

Best,

Ryan Ma

Hi Ryan,

I am combining memory regions because I got the error #10099-D "program will not fit into available memory". I was running tests yesterday and the problem arose when I combined the memory regions. The empty project works well.

Best,

Juan

Dear Ryan,

After trying almost everything, the issue was solved by initializing the .cinit section from the RAMLS_COMB memory.

Best,

Juan Ramón Camarillo

Hi Juan,

Thank you for the update, were you able to do this within syscfg? Could you provide any feedback for the tool?

Best,

Ryan Ma

Hi Ryan,

Yes, I solved the problem using the sysconfig tool. It's been incredibly beneficial, especially for someone like me who isn't a seasoned software developer. Using it made navigating the product much smoother and helped me avoid potential errors.

Best regards,

Juan Ramón Camarillo

Hi Juan,

Thank you for the feedback as it is very valuable for us to know what we could be doing better.

Best of luck with your project,

Ryan Ma