TMS320F28388D: CLA tmplate program does not work on F28388X

Hi LJN,

Which template code are you using from C2000ware? It could be that the symbols aren't being properly loaded. Please see the CLA Software Development Guide "Debugging Tips" section to make sure you are following the proper steps when debugging.

Best Regards,

Delaney

Dear Delaney,

I use the <C2000DIR>\training\device\f2838x\empty_cla_lab template project. I did some step-by-step debugging, and the illegal instruction handler occurred in the memconfig() function of the board.c file.

Sincerely,
LJN

Hi LJN,

Delaney is out of the office today. Please allow for another 1-2 days for a response. Thanks for the patience in the meantime.

Best Regards,

Allison

Hi LJN,

This template project has no initialization code or loop in the main, so it would probably be better to base your code off of/initially test with one of the driverlib examples (located in [C2000ware install]/driverlib/f2838x/examples/c28x/cla/). Then you can start incorporating code from the example into the template code to build your own project. Make sure to follow these steps when loading a project onto both the CPU and the CLA:

1. Launch target configuration
   
   1. both cores should be disconnected
2. "Connect Target" for the c28x
   1. c28x will be suspended  
   2. It may throw an error about not having the debug information at this point, that can be ignored
3. Load the .out file onto the c28x (Run >> Load >> Load Program >> [navigate to the .out file])
   1. c28x will be suspended still
4. "Connect Target" for the CLA
   1. both cores will be suspended
5. Load the .out symbols onto the CLA (Run >> Load >> Load symbols >> [navigate to the .out file])
6. Switch context to the c28x (click on it in the debug window) and Resume
7. If a CLA task get triggered and it has a  __mdebugstop()line, the CLA should then be stopped there

Let me know if you have any questions about any of these steps.

Best Regards,

Delaney

Hi Delaney,

it resolved my problem, thank you a lot. Now I can establish a debugging session with the CLA. Unfortunately, I have another problem related to the available memory in RAM after the configuration of ADC and EPWM. I am not sure if the code exceeds the available space or if the CLA wants to get access to the registers which to it has no access.

May you help me resolve these configuration subjects:
_Firstly, when I open this folder, I notice that the Sysconfig window doesn't contain a Hardware tab on the left side( Can it be a problem when we want to upload it to the ControlCard)? I am using the TMS320F28388D and it is noticed in the CLA LAb that his LSRAM configuration must be according to   https://dev.ti.com/tirex/explore/node?node=A__ATN4mjBEXfMv3bdvcLNMIg__C2000- ACADEMY__3H1LnqB__LATEST  

*LS1RAM-> CLA program memory
*LS5RAM-> CPU/CLA shared data memory
But it results in this Error for the CLA Runing, it becomes suspended:

I tried the following configuration:

LS0RAM -> CPU/CLA shared data memory
LS1RAM -> CPU/CLA shared data memory
LS5RAM -> CLA program memory

and this works, it does not suspend the execution of the CLA. But after I added to the basic CLA folder(located in [C2000ware install]/driverlib/f2838x/examples/c28x/cla/)   ADC and EPWM configuration, the debug couldn't complete and lead to this errors:

*"../2838x_RAM_CLA_lnk_cpu1.cmd", line 76: error #10099-D: program will not fit into available memory, or the section contains a call site that requires a trampoline that can't be generated for this section. placement with alignment/blocking fails for section ".text" size 0x20d6 page 0.  Available memory ranges:

   RAMM0        size: 0x24f        unused: 0x0          max hole: 0x0      
   RAMD0        size: 0x800        unused: 0x0          max hole: 0x0      
   RAMLS2       size: 0x800        unused: 0x0          max hole: 0x0      
   RAMLS3       size: 0x800        unused: 0x0          max hole: 0x0      
   RAMLS4       size: 0x800        unused: 0x0          max hole: 0x0  

*"../2838x_RAM_CLA_lnk_cpu1.cmd", line 77: error #10099-D: program will not fit into available memory, or the section contains a call site that requires a trampoline that can't be generated for this section. placement with alignment/blocking fails for section ".cinit" size 0x18 page 0.  Available memory ranges:

   RAMLS3       size: 0x800        unused: 0x0          max hole: 0x0    

_Lastly, Do I must to configure the CMD( linker CMD tool in SYSCONFIG) when we use CLA(Task1, Task8) for data exchange ?according to: www.ti.com/.../sprad49.pdf

Sincerely,
LJN
 

Hi LJN,

Glad to hear that you are now successfully able to debug on the CLA. Below are the answers to your new questions:

Lukasz Niewiara said:

Firstly, when I open this folder, I notice that the Sysconfig window doesn't contain a Hardware tab on the left side

The hardware tab in Sysconfig is added whenever board support is selected for a Sysconfig project. Adding board support isn't a required step, so you could still run a program on the F2838x ControlCARD without it, as long as the correct GPIO selections are made.

Lukasz Niewiara said:

I am using the TMS320F28388D and it is noticed in the CLA LAb that his LSRAM configuration must be according to

If you are trying to get the CLA Academy lab working, I would suggest starting with the empty CLA lab first as the instructions say which should already have the proper configurations needed (and has board support enabled). If you are trying to build your own code from an existing example, board support is not required.

To clarify, which example in driverlib are you trying to use? Are these errors generated after changing only the LSRAM0 configuration to be CPU/CLA shared data memory in the MEMCFG module of Sysconfig? May I ask why you trying to designate LSRAM0 as shared memory?

Lukasz Niewiara said:

_Lastly, Do I must to configure the CMD( linker CMD tool in SYSCONFIG) when we use CLA(Task1, Task8) for data exchange ?

You would only need to change the configurations in the linker CMD file if you are trying to change how the linker allocates the needed memory for the CPU and CLA onto the different memory blocks. For example, if a CLA program is quite large and doesn't fit in the default LSRAMs chosen. In most cases, this would not be necessary. For running the driverlib examples, I would suggest keeping the linker CMD allocations and MEMCFG configurations as is and just trying to modify the code itself to make your application. Then if your custom application has issues fitting into the memory, you can try to move things around.

Best Regards,

Delaney

Dear Delaney,

Thanks for your help. The project is now building and the program is executed in the MCU. Unfortunately, I have still a problem with the CLA interrupt, it is executed once and later no more. I can't access the CLA interrupt(cla1Isr1). After debugging and starting the project, the CLA part begins in "Running" mode and stops immediately - "Cla1Task1 does not contain frame information". The CPU1 remains in "Running" mode.

The CLA is triggered with the EOC signal. I suppose it may be a problem with not properly configured ADC. Where should be the register cleared for the ADC if I use the CLA? I found some information that the CLA does not have any access to the ADC control registers. May it be related to this issue?

Sincerely,
LJN

Hi LJN,

Lukasz Niewiara said:

Cla1Task1 does not contain frame information

Please see this thread which details the same error.

This is likely due to the CLA program not being allocated correctly in the LSRAM memories. Can you view the .map file and make sure that all of the CLA program is being placed in LSRAM memories that the CLA has access to?

Best Regards,

Delaney

Dear Delaney,

thanks for your reply. I will check the mentioned thread. The applied configuration in sysconfig is as follows:

The map file entry is as follows:

MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  BEGIN                 00000000   00000002  00000002  00000000  RWIX
  BOOT_RSVD             00000002   000001af  00000000  000001af  RWIX
  RAMM0                 000001b1   0000024f  0000024f  00000000  RWIX
  RAMM1                 00000400   000003f8  00000100  000002f8  RWIX
  CLA1_MSGRAMLOW        00001480   00000080  00000004  0000007c  RWIX
  CLA1_MSGRAMHIGH       00001500   00000080  00000000  00000080  RWIX
  RAMLS0                00008000   00000800  00000800  00000000  RWIX
  RAMLS1                00008800   00000800  000001c8  00000638  RWIX
  RAMLS2                00009000   00000800  00000800  00000000  RWIX
  RAMLS3                00009800   00000800  00000800  00000000  RWIX
  RAMLS4                0000a000   00000800  00000800  00000000  RWIX
  RAMLS5                0000a800   00000800  000005c4  0000023c  RWIX
  RAMLS6                0000b000   00000800  00000187  00000679  RWIX
  RAMLS7                0000b800   00000800  00000000  00000800  RWIX

SECTION ALLOCATION MAP

 output                                  attributes/
section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------

(.data)

Cla1Prog   0    0000ac12    000001b2     
                  0000ac12    000000d0     lab_cla_tasks.obj (Cla1Prog:Cla1Task1)
                  0000ace2    0000007c     lab_cla_tasks.obj (Cla1Prog:ADC_readResult)
                  0000ad5e    00000066     lab_cla_tasks.obj (Cla1Prog:Cla1Task8)

Cla1ToCpuMsgRAM
*          0    00001480    00000004     UNINITIALIZED
                  00001480    00000004     lab_main.obj (Cla1ToCpuMsgRAM)

CLAscratch
*          0    00008800    00000100     UNINITIALIZED
                  00008800    00000100     --HOLE--

.bss_cla   0    00008900    00000040     UNINITIALIZED
                  00008900    00000040     lab_cla_tasks.obj (.bss_cla:delay)

.const_cla
*          0    00008940    00000040     
                  00008940    00000040     lab_cla_tasks.obj (.const_cla:coeffs)

.scratchpad
*          0    00008980    00000006     UNINITIALIZED
                  00008980    00000002     lab_cla_tasks.obj (.scratchpad:Cla1Prog:Cla1Task8)
                  00008980    00000004     lab_cla_tasks.obj (.scratchpad:Cla1Prog:ADC_readResult)
                  00008984    00000002     lab_cla_tasks.obj (.scratchpad:Cla1Prog:Cla1Task1)

I did not realize any failure in memory area allocation but found some uninitialized sections. May they be the source of the realized troubles? Should I provide the full .map file ?

If I switch the memory configuration to:

LS0 RAM-> CPU/CLA shared data memory
LS1 RAM-> CPU/CLA shared data memory
LS5 RAM-> CLA program memory

I obtained the error "ADC Result does not contain frame information"

Sincerely yours,
LJN

Hi LJN,

Yes, these uninitialized sections would definitely be an issue. All of these should be defined in the linker cmd file. Can you make sure you didn't remove any of these allocations and compare your linker cmd to one of the example CLA linker cmd files?

I would also suggest gaining a full understanding of the linker cmd file before trying to make modifications. The following resource would be helpful to take a look at.

Best Regards,

Delaney

Dear Delaney,

I configured the TMS320F28388D with the SYSCFG using the ControlCard, according to the CLA examples that I was referred to, but I do not have any CMD configuration set in their SYSCFG. Could you indicate where can I find some CMD file examples, are they located in the C2000ware folders?

I suppose that because of the lack of a CMD file, the linker is unable to indicate the proper memory area for the CLA program and data memory sections. I understand the origin of the problem, but for now, I am not able to use SYSCONFIG to properly generate a CMD file accordingly to the MEMCONFIG section.

Sincerely,
LJN

Hi LJN,

Sure, below are some resources that should be helpful.

All of the different linker command files provided by C2000ware for the F2838x are located in the folder path: [C2000ware install]/device_support/f2838x/common/cmd/. You could use these to compare and understand the different linker cmd configurations.

The Syconfig Linker Command Tool guide is also linked here. If you include the CMD module in Sysconfig, this generates a linker cmd file with Sysconfig. 

Let me know if these resources help.

Best Regards,

Delaney

Dear Delaney,

the resources helped - the modification of CMD file results in a proper memory allocation in the generated code.

I have one minor issue with the ClaISR function, for some reason, when it is linked to the ADC.

The system is configured as follows, the EPWM module triggers the SOC for ADC, and after conversion, the EOC should trigger the ClaISR. But it does not. The ClaISR is only executed if the input voltage on the ADC channel becomes about 1.5 V (the middle of the ADC's reference voltage). It is like some interrupt acknowledgment was not made, and no consecutive ADC conversions were not made, resulting in no ClaISR triggering.

I found some information that the CLA can not access all registers for the ADC. May it be related to this issue?

Sincerely,
LJN

Hi LJN,

I have a few followup questions:

• By "ClaISR" are you referring to an interrupt on the c28x side that is being triggered by the completion of a CLA task? Or are you referring to the CLA task execution itself (which is basically an "interrupt" on the CLA) which can be triggered by the ADC EOC?
• Can you refer to the CLA ADC example in [C2000ware install]/driverlib/f2838x/examples/c28x/cla/cla_ex5_adc_just_in_time? I believe it is executing a similar functionality.

Lukasz Niewiara said:

I found some information that the CLA can not access all registers for the ADC. May it be related to this issue?

• Can you point me to where you found the above information and I will look into it?

Best Regards,

Delaney

Dear Delaney,

I am referring to an interrupt on the c28x side that is being triggered by the completion of a CLA task. For some reason, the interrupt register flags are set but the interrupt is not executed.

I will check the example, maybe it can resolve my issues.

About the ADC registers I found information that the CLA can access directly only the ADC result registers, but not the ADC control registers. For now, I am not able to find back the thread where I read this information. If I do, I will send you a reference to it.

Sincerely,
LJN

Hi LJN,

Lukasz Niewiara said:

I am referring to an interrupt on the c28x side that is being triggered by the completion of a CLA task. For some reason, the interrupt register flags are set but the interrupt is not executed.

I see, can you check the following:

• Is the correct ACK group being cleared at the end of the ISR?
• Are you enabling interrupts globally using an EINT call?
• Is the IER (interrupt enable) set for the interrupt group as well as for the specific interrupt channel in the PIE? 
• Is the IFR (interrupt flag) being set for the interrupt group as well as for the specific interrupt channel in the PIE?
• Are you registering your ISR?

For CLA task 1, the interrupt group is 11 and the interrupt channel is 1.

Let me know if the example helps resolve your issues.

Best Regards,

Delaney

Hi LJN,

Any updates? Were you able to resolve the issue by referring to the example? If so, please upvote any of my previous responses that were helpful.

Best Regards,

Delaney