TMS320F28384D: CPU does not start up according to datasheet

Ito,

K.Z said:

・After 3.3V starts up, 1.2V starts up about 200ms later.
When external reset is input about 530ms after that, the CPU does not start up.

The CPU never starts when this is done? How are you determining whether the CPU has correctly booted? Do you have some simple test code in flash? 

Also, is XRSn being driven high externally somehow? XRSn should be treated as open-drain, so it should be driven low and simply released to go high.

Best Regards,

Ben Collier

Hi Collier,

Thank you for your reply.

>The CPU never starts when this is done? How are you determining whether the CPU has correctly booted?
→
Yes, CPU did not boot.
My custermer has determined that the CPU has booted when the software boots normally and the 7segLED displays normally.

>>Also, is XRSn being driven high externally somehow? XRSn should be treated as open-drain, so it should be driven low and simply released to go high.
→
The customer is currently unable to output in open drain, so they are driving with totem pole output.
However, the customer believes that the power supply is 3.3V, the same as VCCIO, and therefore is not applying a high voltage.

Best Regards,

Ito

Ito,

Why are they able to use totem pole output, but not open drain? 

Are you able to share the schematic for the VDD, VDDIO, and XRSn pins? 

Best Regards,

Ben Collier

Hi Collier,

They did not realize at the time of design that it had to be open drain.
I will send you the schematic, please enable private message.

ito

Just accepted the friend request. 

Hi Collier,

I sent you the schematic.

The component that is the totem pole output is a TOSHIBA TC7SZ08FE.

And I found another possible cause.

The 3.3V is generated from 5V, but there is an e-fuse (TPS16630) in between.
When this e-fuse was removed (short), the CPU booted.
The waveform at that time is shown in the following image.

Looking at the waveform (purple) of the 5V output of the e-fuse,
the current limit dropped by about 1V at the moment the power supply IC started up.
I would think that this phenomenon would not affect the 3.3V rise.

Next, compare the waveforms with e-fuse installed and without,
The position of the rise of 3.3V (green) seems to be different.
Could this be the cause?

Best Regards,

Ito

Ito,

Could you still check to see where 3.3V is being probed? How close to the device pin is this being probed? 

From your test, it looks like the eFUSE limiting current is the problem, but the 3.3V and 1.2V rails still look acceptable. I wonder if we would see something different depending on where 3.3V is being probed.

Also, the customer needs to make sure that open drain circuit as described in the data sheet is used in their final design. If the device tries to force XRSn low while the Totem Pole is forcing XRSn high, the device could be damaged.

Just curious, is it a problem for the customer that they need to wait 700ms for XRSn to be released? Or is the problem that the customer is worried about the device not booting at all if their timing is wrong for releasing the reset? 

If the latter is the case, then changing the XRSn circuit to open-drain will probably fix their issue. I would bet that in the case where the device never boots, it is trying to reset, but cannot drive XRSn low, so it never boots. If possible, it would be great if they could make this change to their board for debugging. If they could remove the totem pole output and replace it with a pullup resistor and a BJT transistor, that would be great.

Best Regards,

Ben Collier

Hi Collier,

>>Could you still check to see where 3.3V is being probed? How close to the device pin is this being probed?
→
It was probed as close as possible to the device pins.

[Current customer problems]

Originally, there was a problem with the CPU not booting when the time that XRSn releases changed, despite the sequence following the datasheet.
The customer would like to determine the cause of this problem. And we want to know the correct sequence.

[Change to open drain]

The customer understands that it must be open drain.
We will change to open drain the next time we change the board.

Will changing to open drain solve the [ problem of CPU not booting when changing the time XRSn is released ] ?

[Another problem]

The customer is making the change to open drain and confirming the sequence for the next development.
According to the data sheet,
・Start up 3.3V faster than 1.2V.
・XRSn is set to low until 3.3V and 1.2V are stable.
If these are satisfied, can I interpret that the CPU will start up even if the minimum slew rate is not satisfied?

Best Rgards,

Ito

Hi,

K.Z said:

Will changing to open drain solve the [ problem of CPU not booting when changing the time XRSn is released ] ?

I think that changing to open drain will solve this problem. I have a guess for what their problem is, which I shared in my last post, but I cannot be sure until they test it by making this change. 

K.Z said:

The customer is making the change to open drain and confirming the sequence for the next development.
According to the data sheet,
・Start up 3.3V faster than 1.2V.
・XRSn is set to low until 3.3V and 1.2V are stable.
If these are satisfied, can I interpret that the CPU will start up even if the minimum slew rate is not satisfied?

This is correct.

Best Regards,

Ben Collier

Hi Collier,

Thank you for your reply.

We will make changes to the open drain in the future and design with the datasheet.
The remaining problem is that the waveform changes with and without e-FUSE.
I would like to identify the cause of this problem, what kind of verification should I do?

Best Regards,

Ito

Hi Collier,

Thank you for your reply.

We will verify after changing to open drain.

Best Regards,

Ito