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TMS320F280025C: ADC Clock Prescaler || maximum frequency of ADC

Part Number: TMS320F280025C

Hi,

I configured ADC Clock Prescaler to (input clock)/1.0 (meaning ADCCLK = SYSCLK) I received warning 

But its working, I measure conversion time via take time stamp (CPUTimer ) --> forceSOC --> while(ADC_isBusy(ADCA_BASE)) -->take second time stamp (CPUTimer ) and measured ~23Clock cycles instead of ~33Clockcycles  when change  ADC Clock Prescaler to (input clock)/2.0 ;

If working ADCCLK = (input clock) / 2.0 (see down example from ADC guide) 



Also, from datasheet of TMS320F28002x Real-Time Microcontrollers (SPRUIN7C) in page 1572 its look like its ok to choose ADCCTL2.PRESCALE 0 (ADCCLK =SYSCLK)  and reduce tEOC by almost half:


So can I  work with my settings? if its not allowed so why its only warning and not error? does it effect other functionality?

Thanks!
Michael

  • Hello Michael,

    PRESCALE of 0 is not a valid setting on this device running at 100MHz. The timing table in the TRM is a generic table that applies to the IP-- for example, if you clocked the CPU at 50MHz instead of 100MHz, then PRESCALE=0 would be valid.

    The ADC will "work" at this frequency, but the accuracy of conversion results is likely to be bad/there will be sources of error.

    Best regards,
    Ibukun