TMS320F28379D: Stuck in Fapi_setActiveFlashBank

Zvi,

I've been made aware of a new condition regarding the use of Fapi_setActiveFlashBank() and the flash prefetch buffer.  If the flash prefetch buffer is active when Fapi_setActiveFlashBank() is called it can result in a ITRAP like you are seeing.  The reason is that Fapi_setActiveFlashBank() function disables the prefetch buffer as well, but if there are still pending instructions from the buffer we can then fetch the trap.

The solution is to disable the pre-fetch buffer from code executing in RAM, and force a pipeline flush, so that no remaining code is in the buffer.

I've C/P the code below for both enable and disable.  Disable needs to be called before any change in Active Flash Bank.  Enable is just to give complementary function that does the same flush, etc.

#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#else
#pragma CODE_SECTION(Flash_DisablePrefetch_SW_Workaround, ".TI.ramfunc");
#endif
void Flash_DisablePrefetch_SW_Workaround(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ASSERT(Flash_isCtrlBaseValid(ctrlBase));

    //
    // Disable flash prefetch
    //
    Flash_disablePrefetch(ctrlBase);

    //
    // Force a pipeline flush to ensure that the write to the last register
    // configured occurs before returning.
    //
    FLASH_DELAY_CONFIG;
}

/* Below is the code for Flash_EnablePrefetch_SW_Workaround()  */

//*****************************************************************************
//
//! Enables flash prefetch mechanism and adds 7 cycle delay
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************

#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#else
#pragma CODE_SECTION(Flash_EnablePrefetch_SW_Workaround, ".TI.ramfunc");
#endif
void Flash_EnablePrefetch_SW_Workaround(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ASSERT(Flash_isCtrlBaseValid(ctrlBase));

    //
    // Disable flash prefetch
    //
    Flash_enablePrefetch(ctrlBase);

    //
    // Force a pipeline flush to ensure that the write to the last register
    // configured occurs before returning.
    //
    FLASH_DELAY_CONFIG;
}

Best,
Matthew